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參數(shù)資料
| 型號： | AT17LV256A |
| 廠商： | Atmel Corp. |
| 英文描述： | 256K FPGA Configuration EEPROM Memory(256K 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) |
| 中文描述： | 256K FPGA配置存儲器（256K現(xiàn)場可編程門陣列（FPGA）的配置的EEPROM存儲器） |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 227K |
| 代理商： | AT17LV256A |
AT17C/LV65A/128A/256A
3
The first AT17A Series Configurator (whose nCS input is
directly driven by the FPGA) provides the first stream of
data to the FPGA device during multi-device configuration.
Once the first AT17A Series device finishes sending config-
uration data, it drives its nCASC pin Low, which drives the
nCS pin of the second AT17A Series device Low. This
allows the second AT17A Series device to send configura-
tion data to the FPGA.
If the nCS pin on the first AT17A Series device is driven
High before all configuration data is transferred
—
or if nCS
is not driven High after all configuration data is trans-
ferred
—
nSTATUS is driven Low, indicating a configuration
error.
The low density AT17A Series Configuration EEPROMs
are not designed to act as system masters (i.e. provide
clock pulses on the serial bus to other devices). Clocking
must be supplied by an FPGA device, a high-density
AT17A Series device (Figure 2), or an external oscillator.
Figure 1.
FPGA device configured with a single AT17A Series Configurator.
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Reset polarity must be set active Low.
Figure 2.
FPGA device configured with multiple AT17A Series Configurators.
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Reset polarity must be set active Low.
3. RC filter recommended for input to nCONFIG to delay configuration (100 ms to 200 ms) until V
CC
is stable within its normal
operating range. (nCONFIG can instead be connected to an active Low system reset signal).
4. Use of the READY pin is optional.
nCONFIG
nS/P
MSEL0
MSEL1
DCLK
DATA0
CONF_DONE
nSTATUS
DCLK
DATA
nCS
OE
AT17C65(A)/128(A)/256(A)
AT17LV65(A)/128(A)/256(A)
EPF8K
GND
VCC
VCC
VCC
VCC
nCONFIG
nS/P
MSEL0
MSEL1
DCLK
DATA0
CONF_DONE
nSTATUS
DCLK
DATA
nCS
OE
AT17C512A/010A
AT17LV512A/010A
Device 1
EPF10K
GND
GND
nCASC
READY
DCLK
DATA
nCS
OE
AT17C65(A)/128(A)/256(A)
AT17LV65(A)/128(A)/256(A)
Device 2
VCC
VCC
VCC
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| AT17LV512 | 512K FPGA Configuration EEPROM Memory(512K 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) |
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| AT22LV10-20JC | Circular Connector; No. of Contacts:12; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:32; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:32-6 RoHS Compliant: No |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10JC | 功能描述:IC SRL CONFG EEPROM 256K 20-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產品變化通告:Product Discontinuation 28/Jul/2010 標準包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-TSOP 包裝:管件 |
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