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參數(shù)資料
| 型號(hào)： | AT17LV256A |
| 廠商： | Atmel Corp. |
| 英文描述： | 256K FPGA Configuration EEPROM Memory(256K 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）配置EEPROM存儲(chǔ)器) |
| 中文描述： | 256K FPGA配置存儲(chǔ)器（256K現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）的配置的EEPROM存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大小： | 227K |
| 代理商： | AT17LV256A |
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AT17C/LV65A/128A/256A
2
Block Diagram
Device Configuration
The control signals for the configuration EEPROM
—
nCS,
OE, and DCLK
—
interface directly with the FPGA device
control signals. All FPGA devices can control the entire
configuration process and retrieve data from the configura-
tion EEPROM without requiring an external intelligent
controller.
The configuration EEPROM device
’
s OE and nCS pins
together control the tri-state buffer on the DATA output pin
and enable the address counter. When OE is driven Low,
the configuration EEPROM resets its address counter and
tri-states its DATA pin. The nCS pin also controls the out-
put of the AT17A Series Configurator. If nCS is held High
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is subsequently
driven Low, the counter and the DATA output pin are
enabled. When OE is driven Low again, the address
counter is reset and the DATA output pin is tri-stated,
regardless of the state of nCS.
When the Configurator has driven out all of its data and
nCASC is driven Low, the device tri-states the DATA pin to
avoid contention with other Configurators. Upon power-up,
the address counter is automatically reset.
This document discusses the EPF8K and EPF10K device
interfaces. For more details or information on other Altera
applications, please reference the
“
AT17A Series Conver-
sions from Altera FPGA Serial Configuration Memories
”
application note.
FPGA Device Configuration
FPGA devices can be configured with a low-density AT17A
Series EEPROM (Figure 1). The AT17A Series device
stores configuration data in its EEPROM array and clocks
the data out serially according to an external clock source.
The OE, nCS, and DCLK pins supply the control signals for
the address counter and the output tri-state buffer. The
AT17A Series device sends a serial bitstream of configura-
tion data to its DATA pin, which is connected to the DATA0
input pin on the FPGA device.
When configuration data for an FPGA device exceeds the
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together (Figure 2).
When multiple AT17A Series devices are required, the
nCASC and nCS pins provide handshaking between the
cascaded EEPROMs.
Note:
A single AT17C/LV65A may only be used at the end of a
cascade chain or as a standalone device.
DCLK
OE
nCS
nCASC
DATA
POWER ON
RESET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10JC | 功能描述:IC SRL CONFG EEPROM 256K 20-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
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