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參數資料
| 型號： | ASMP5P23S04A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3 V SpreadTrak Zero Delay Buffer |
| 中文描述： | 3.3伏SpreadTrak零延遲緩沖器 |
| 文件頁數： | 8/13頁 |
| 文件大小： | 226K |
| 代理商： | ASMP5P23S04A |
``
August 2004
ASM5P23S04A
rev 2.0
3.3
‘SpreadTrak’ Zero Delay Buffer
8
Notice: The information in this document is subject to change without notice.
Switching Characteristics for ASM5I23S04A Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t
1
Output Frequency
30-pF load, All devices
10
100
MHz
t
1
Output Frequency
20-pF load, -1H, -5H devices
10
133.3
MHz
t
1
Output Frequency
15-pF load, -1 and -2 devices
10
133.3
MHz
Duty Cycle
4
= (t
2
/ t
1
) * 100
(-1, -2, -1H, -5H)
Measured at 1.4V, F
OUT
= <66.66 MHz
30-pF load
40.0
50.0
60.0
%
Duty Cycle
4
= (t
2
/ t
1
) * 100
(-1, -2, -1H, -5H)
Measured at 1.4V, F
OUT
= <50 MHz
15-pF load
45.0
50.0
55.0
%
t
3
Output Rise Time
4
(-1, -2)
Measured between 0.8V and 2.0V
30-pF load
2.50
ns
t
3
Output Rise Time
4
(-1, -2)
Measured between 0.8V and 2.0V
15-pF load
1.50
ns
t
3
Output Rise Time
4
(-1H, -5H)
Measured between 0.8V and 2.0V
30-pF load
1.50
ns
t
4
Output Fall Time
4
(-1, -2)
Measured between 2.0V and 0.8V
30-pF load
2.50
ns
t
4
Output Fall Time
4
(-1, -2)
Measured between 2.0V and 0.8V
15-pF load
1.50
ns
t
4
Output Fall Time
4
(-1H, -5H)
Measured between 2.0V and 0.8V
30-pF load
1.25
ns
Output-to-output skew on same bank (-1, -2)
4
All outputs equally loaded
200
Output-to-output skew
(-1H, -5H)
All outputs equally loaded
200
Output bank A -to- output bank B skew (-1, -5H)
All outputs equally loaded
200
t
5
Output bank A -to- output bank B skew (-2)
All outputs equally loaded
400
ps
t
6
Delay, REF Rising Edge to FBK Rising Edge
4
Measured at V
DD
/2
0
±250
ps
t
7
Device-to-Device Skew
4
Measured at V
DD
/2 on the FBK pins of the device
0
500
ps
t
8
Output Slew Rate
4
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/ns
Measured at 66.67 MHz, loaded outputs,
15 pF load
180
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
t
J
Cycle-to-cycle jitter
4
(-1, -1H, -5H)
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
ps
Measured at 66.67 MHz, loaded outputs, 30pF load
400
t
J
Cycle-to-cycle jitter
4
(-2)
Measured at 66.67 MHz, loaded outputs,
15 pF load
380
ps
t
LOCK
PLL Lock Time
4
Stable power supply, valid clock presented on REF
and FBK pins
1.0
ms
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