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參數(shù)資料
| 型號： | ASMP5P23S04A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3 V SpreadTrak Zero Delay Buffer |
| 中文描述： | 3.3伏SpreadTrak零延遲緩沖器 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 226K |
| 代理商： | ASMP5P23S04A |
``
August 2004
ASM5P23S04A
rev 2.0
3.3
‘SpreadTrak’ Zero Delay Buffer
2
Notice: The information in this document is subject to change without notice.
ASM5P23S04A Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P23S04A-1
Bank A or Bank B
Reference
Reference
ASM5P23S04A-1H
Bank A or Bank B
Reference
Reference
ASM5P23S04A-2
Bank A
Reference
Reference /2
ASM5P23S04A-2
Bank B
2 X Reference
Reference
ASM5P23S04A-5H
Bank A or Bank B
Reference /2
Reference /2
‘SpreadTrak’
Many systems being designed now utilize a
technology called Spread Frequency Timing
Generation. ASM3P23S04A is designed so as not
to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the Spread
Spectrum feature through, the result is a significant
amount of tracking skew which may cause
problems in the systems requiring synchronization.
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
0
-500
-1000
-1500
500
1000
1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
R
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
相關(guān)PDF資料 |
PDF描述 |
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| ASMP5P23S05A | 3.3V SpreadTrak Zero Delay Buffer |
| ASMP5P23S09A | 3.3V SpreadTrak Zero Delay Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASMP5P23S05A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V SpreadTrak Zero Delay Buffer |
| ASMP5P23S09A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V SpreadTrak Zero Delay Buffer |
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| ASMP-CWH0-ZDFG2 | 功能描述:LED CHIPLED RA 0603 SMD 制造商:broadcom limited 系列:* 零件狀態(tài):初步 標(biāo)準(zhǔn)包裝:4,000 |
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