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參數(shù)資料
| 型號： | ASMP5P23S04A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3 V SpreadTrak Zero Delay Buffer |
| 中文描述： | 3.3伏SpreadTrak零延遲緩沖器 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 226K |
| 代理商： | ASMP5P23S04A |
``
August 2004
ASM5P23S04A
rev 2.0
3.3
‘SpreadTrak’ Zero Delay Buffer
3
Notice: The information in this document is subject to change without notice.
To close the feedback loop of the ASM5P23S04A,
the FBK pin can be driven from any of the four
available output pins. The output driving the FBK pin
will be driving a total load of 7 pF plus any additional
load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the
input output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all
outputs including the one providing feedback should
be equally loaded. If input-output delay adjustments
are required, use the above graph to calculate
loading differences between the feedback output and
remaining outputs. For zero output-output skew, be
sure to load outputs equally.
Pin Configuration
Pin Description for ASM5P23S04A
Pin #
Pin Name
Description
1
REF
1
Input reference frequency, 5V tolerant input
2
CLKA1
2
Buffered clock output, bank A
3
CLKA2
2
Buffered clock output, bank A
4
GND
Ground
5
CLKB1
2
Buffered clock output, bank B
6
CLKB2
2
Buffered clock output, bank B
7
V
DD
3.3V supply
8
FBK
PLL feedback input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
1
2
3
4
REF
CLKA1
CLKA2
CLKB1
CLKB2
V
DD
GND
FBK
ASM5P23S04A
8
7
6
5
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PDF描述 |
|---|---|
| ASMP5P23S05A | 3.3V SpreadTrak Zero Delay Buffer |
| ASMP5P23S09A | 3.3V SpreadTrak Zero Delay Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASMP5P23S05A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V SpreadTrak Zero Delay Buffer |
| ASMP5P23S09A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V SpreadTrak Zero Delay Buffer |
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