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參數(shù)資料
| 型號： | ASM5I9774A-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| 中文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, TQFP-52 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 477K |
| 代理商： | ASM5I9774A-52-ER |
June 2005
rev 0.3
ASM5I9774A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
7 of 12
Notice: The information in this document is subject to change without notice.
AC Electrical Specifications
(VDD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
1
Parameter
Description
Condition
Min
Typ
Max
Unit
f
VCO
VCO Frequency
200
-
400
MHz
÷8 Feedback
25
-
50
÷12 Feedback
16.6
-
33.3
÷16 Feedback
12.5
-
25
÷24 Feedback
8.3
-
16.6
÷32 Feedback
6.3
-
12.5
÷48 Feedback
Bypass mode
(PLL_EN = 0)
4.2
-
8.3
f
in
Input Frequency
0
-
200
MHz
f
refDC
Input Duty Cycle
25
-
75
%
t
r
, t
f
TCLK Input Rise/FallTime
0.7V to 1.7V
–
-
1.0
nS
÷4 Output
50
-
100
÷8 Output
25
-
50
÷12 Output
16.6
-
33.3
÷16 Output
12.5
-
25
f
MAX
Maximum Output Frequency
÷24 Output
8.3
-
16.6
MHz
DC
Output Duty Cycle
45
-
55
%
t
r
, t
f
Output Rise/Fall times
0.7V to 1.8V
0.1
-
0.75
nS
t
(
φ
)
Propagation Delay
(static phase offset)
TCLK to FB_IN, does
not include jitter
–100
-
100
pS
t
sk(O)
Output-to-Output Skew
Skew within Bank
Banks at same
frequency
Banks at different
frequency
-
-
150
pS
-
-
150
t
sk(B)
Bank-to-Bank Skew
-
-
200
pS
t
PLZ, HZ
Output Disable Time
-
-
10
nS
t
PZL, ZH
Output Enable Time
PLL Closed Loop Bandwidth
(–3 dB)
-
-
10
nS
BW
-
0.5 -1.0
-
MHz
Same frequency
-
-
100
t
JIT(CC)
Cycle-to-Cycle Jitter
Multiple frequencies
-
-
250
pS
t
JIT(PER)
Period Jitter
-
-
100
pS
t
JIT(
φ
)
I/O Phase Jitter
-
-
125
pS
t
LOCK
Maximum PLL Lock Time
-
-
1
mS
Note: 1. AC characteristics apply for parallel output termination of 50
to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9774A-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775A | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775A-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775AG-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9774A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9775A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
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