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參數(shù)資料
| 型號(hào)： | ASM5I9774A-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| 中文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, TQFP-52 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 477K |
| 代理商： | ASM5I9774A-52-ER |
June 2005
rev 0.3
‘SpreadTrak’
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM59774A is designed so as not to filter off the Spread
Spectrum feature of the Reference Input, assuming it
exists.
ASM5I9774A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
4 of 12
Notice: The information in this document is subject to change without notice.
When a zero delay buffer is not designed to pass the
Spread Spectrum feature through, the result is a
significant amount of tracking skew which may cause
problems in the systems requiring synchronization.
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
÷8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
÷12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 33.3 MHz
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 25 MHz
÷24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 16.6 MHz
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 12.5 MHz
÷48
Input Clock * 48
4.2 MHz to 10.4 MHz
4.2 MHz to 8.3 MHz
Table 2. Function Table (configuration controls)
Control
Default
0
1
TCLK_SEL
0
TCLK0
TCLK1
VCO_SEL
0
VCO÷2 (high input frequency range)
VCO÷4 (low input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL
feedback loop is open and the VCO running at its
minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during
power-up.
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
PLL enabled. The VCO output
connects to the output dividers
MR#/OE
1
Outputs enabled
CLK_STP#
1
Outputs enabled
Table 3. Function Table (Bank A, B and C)
VCO_SEL
SELA
QA(4:0)
SELB
QB(4:0)
SELC
QC(3:0)
0
0
÷4
0
÷4
0
÷8
0
1
÷8
1
÷8
1
÷12
1
0
÷8
0
÷8
0
÷16
1
1
÷16
1
÷16
1
÷24
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9774A-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775A | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775A-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775AG-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9774A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9775A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
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