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參數(shù)資料
| 型號(hào)： | ASM5I9775A-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| 中文描述： | 9775 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, TQFP-52 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 507K |
| 代理商： | ASM5I9775A-52-ER |
June 2005
rev 0.3
ASM5I9775A
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
General Features
Output frequency range: 8.3MHz to 200MHz
Input frequency range: 4.2MHz to 125MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 pS max output-output skew
PLL bypass mode
‘SpreadTrak’
Output enable/disable
Industrial temperature range: –40°C to +85°C
52 Pin 1.0 mm TQFP Package
RoHS Compliance
Functional Description
The ASM5I9775A is a low-voltage high-performance
200 MHz PLL-based zero delay buffer designed for high-
speed clock distribution applications. The ASM5I9775A
features two reference clock inputs and provides
Block Diagram
14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while
Bank C divides by 8 or 12 per SEL(A:C) settings, see
Functional Table
. These dividers allow output to input
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
LVCMOS compatible output can drive 50
series or
parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one
or two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable, given that the VCO is
configured to run between 200 MHz and 500 MHz. This
allows a wide range of output frequencies from 8.3 MHz
to 200 MHz. For normal operation, the external feedback
input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the
input reference clock set by the feedback divider, see
Frequency Table.
When PLL_EN is LOW, PLL is
bypassed and the reference clock directly feeds the
output dividers. This mode is fully static and the minimum
input clock frequency specification does not apply.
.
CLK
STOP
CLK
STOP
CLK
STOP
+2/+4
+2/+4
+4/+6
+4/+6/+8/+12
PLL
200-
500MHZ
VCO_SEL (1, 0)
QC3
QC2
QC1
QC0
QB3
QB4
QB2
QB1
QB0
QA3
QA4
QA2
QA1
QA0
FB_OUT
+2
+4
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
SELA
SELB
SELC
CLK_STP#
FB_SEL(1.0)
MR#/OE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9775A-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775AG-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775AG-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5P2304A-1H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304A-1H-08-SR | 3.3 V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9775A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5P2304A | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2304A-1-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
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