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參數(shù)資料
| 型號： | ASM2I99448G-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| 中文描述： | 99448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 594K |
| 代理商： | ASM2I99448G-32-ET |
May 2005
rev 0.3
Table 6. AC CHARACTERISTICS
(V
CC
= 3.3V ± 5%, T
A
= –40°C to +85°C)
1
ASM2I99448
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
5 of
15
Symbol
f
ref
f
MAX
V
PP
V
CMR
t
P, REF
t
r
, t
f
t
PLH/HL
t
PLH/HL
t
PLZ, HZ
t
PZL, LZ
Characteristics
Min
0
0
400
1.3
1.4
Typ
Max
350
350
1000
V
CC
-0.8
Unit
MHz
MHz
mV
V
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
pS
nS
pS
pS
%
nS
Condition
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
CCLK Input Rise/Fall Time
PCLK
PCLK
LVPECL
LVPECL
2
1.0
3
3.6
3.3
11
11
0.8 to 2.0V
Propagation delay
PCLK to any Q
CCLK to any Q
1.6
1.3
Output Disable Time
Output Enable Time
t
S
Setup time
CCLK to CLK_STOP
PCLK to CLK_STOP
0.0
0.0
1.0
1.5
t
H
Hold time
CCLK to CLK_STOP
PCLK to CLK_STOP
t
sk(O)
Output-to-output Skew
Device-to-device Skew
Output pulse skew
4
Output Duty Cycle
Output Rise/Fall Time
150
2.0
300
400
55
1.0
t
sk(PP)
t
SK(P)
DC
Q
t
r
, t
f
PCLK or CCLK to any Q
Using CCLK
Using PCLK
f
Q
<170 MHz
45
0.1
50
DC
REF
= 50%
0.55 to 2.4V
Note: 1. AC characteristics apply for parallel output termination of 50
to V
TT
.
2. V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts t
PLH/HL
and t
SK(PP)
.
3. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse
width, output duty cycle and maximum frequency specifications.
4. Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
- t
pHL
|.
Table 7. DC CHARACTERISTICS
(V
CC
= 2.5V ± 5%, T
A
= –40°C to +85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR
Characteristics
Min
1.7
-0.3
250
1.0
Typ
Max
V
CC
+ 0.3
0.7
Unit
V
V
mV
V
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
V
IN
=GND or
V
IN
=VCC
I
OH
= -15 mA
3
I
OL
= 15 mA
3
All V
CC
Pins
Input high voltage
Input low voltage
Peak-to-peak input voltage
Common Mode Range
PCLK
PCLK
1
V
CC
-0.7
I
IN
Input current
2
300
μA
V
OH
V
OL
Z
OUT
I
CCQ
Output High Voltage
Output Low Voltage
Output impedance
Maximum Quiescent Supply Current
Note: 1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range and the input swing lies within the V
(DC) specification.
2. Input pull-up / pull-down resistors influence input current.
3. The ASM2I99448 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
. Alternatively, the device drives one 50
series terminated transmission lines at V
CC
=2.5V.
4. I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
1.8
V
V
mA
0.6
19
4
2.0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ASM2I99448G-32-LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99456 | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V/2.5V LVCMOS Clock Fanout Buffer |
| ASM2I99456-32-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS Clock Fanout Buffer |
| ASM2I99456-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS Clock Fanout Buffer |
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