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參數(shù)資料
| 型號： | ASM2I99448G-32-LR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CAP CERM 470PF 500V X7R 10% 1206 |
| 中文描述： | 99448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, LQFP-32 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 594K |
| 代理商： | ASM2I99448G-32-LR |
May 2005
rev 0.3
ASM2I99448
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Features
12 LVCMOS compatible clock outputs
Selectable LVCMOS and differential LVPECL
compatible clock inputs
Maximum clock frequency of 350MHz
Maximum clock skew of 150pS
Synchronous output stop in logic low state
eliminates output runt pulses
High–impedance output control
3.3V or 2.5V power supply
Drives up to 24 series terminated clock lines
Ambient temperature range –40°C to +85°C
32–Lead LQFP & TQFP packaging
Supports
clock
distribution
in
networking,
telecommunication and computing applications
Pin and Function compatible to MPC9448 and
MPC948
Functional Description
The ASM2I99448 is a 3.3V or 2.5V compatible, 1:12 clock
fanout buffer targeted for high performance clock tree
applications. With output frequencies up to 350 MHz and
output skews less than 150 pS, the device meets the needs
of most demanding clock applications.
The ASM2I99448 is specifically designed to distribute
LVCMOS compatible clock signals up to a frequency of
350MHz. Each output provides a precise copy of the input
signal with a near zero skew. The outputs buffers support
driving of 50
terminated transmission lines on the incident
edge: each output is capable of driving either one parallel
terminated or two series terminated transmission lines.
Two selectable, independent clock inputs are available,
providing support of LVCMOS and differential LVPECL
clock distribution systems. The ASM2I99448 CLK_STOP
control is synchronous to the falling edge of the input clock.
It allows the start and stop of the output clock signal only in
a logic low state, thus eliminating potential output runt
pulses. Applying the OE control will force the outputs into
high–impedance mode.
All inputs have an internal pull–up or pull–down resistor
preventing unused and open inputs from floating. The
device supports a 2.5V or 3.3V power supply and an
ambient temperature range of –40°C to +85°C. The
ASM2I99448
is
pin
and
function
compatible
but
performance–enhanced to the MPC948.
相關PDF資料 |
PDF描述 |
|---|---|
| ASM2I99448G-32-LT | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448 | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-ER | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-ET | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-LR | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ASM2I99448G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99456 | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V/2.5V LVCMOS Clock Fanout Buffer |
| ASM2I99456-32-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS Clock Fanout Buffer |
| ASM2I99456-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS Clock Fanout Buffer |
| ASM2I99456-32-LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS Clock Fanout Buffer |
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