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參數資料
| 型號： | ASCELL3911 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 通信及網絡 |
| 英文描述： | ER 6C 6#16 SKT RECP LINE |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數： | 4/13頁 |
| 文件大?。?/td> | 104K |
| 代理商： | ASCELL3911 |
ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet
ASCell3911
Rev. A, February 2000
Page 4 of 13
Austria Mikro Systeme International AG
Note: CRYSTAL and RANGE are bits of the control information.
1.2
The microprocessor clock frequency F
CLK
is generated by dividing the XTAL frequency F
XOSC
by
4 if CRYSTAL is ′L′ and by dividing the XTAL frequency F
XOSC
by 6 if CRYSTAL is ′H′.
Microprocessor Clock
Note: CRYSTAL is one bit of the control information.
1.3
The SC3011 uses FSK modulation with a frequency deviation of
≈
60 kHz at a gross data rate
from 18,25 kbit/s for the 868,300 MHz ISM band.
In the transmitter, the data from the pulse interference resistant protocol encoder is first trans-
formed into a complex base-band signal in the sin/cos block. After filtering it is shifted up to RF in
an I/Q based direct conversion transmitter.
Modulation
1.4
In order to avoid disturbance due to pulsed interferes, e.g. GSM phones, the net data block is
encoded with a special protocol. Up to two simultaneous GSM disturbers can be handled by
adding redundancy to the FSK data in a suitable manner.
The 128 bits of a message (net data block) are put into a transmission sequence that alternates
a synchronization packet and data packet at transmission as shown in Figure 2.
To form a data packet, the 128 bit net data the information is split in 16 bytes where a bytenum-
ber and a parity is added to generate 14 bit words. Therefore the 128 bits of net data are ex-
panded to the 224 bit long (gross) data packet. The synchronization packet is simple 0101-
sequence of 252 bit.
Burst interference Resistant Protocol Encoder
Transmission Protocol
W
0
W
1
W
2
W
3
W
4
W
5
W
6
W
7
W
8
W
9
W
10
W
11
W
12
W
13
W
14
W
15
Word Pattern in Data Packet
Data Packet
W
0
. . . W
15
SYNC
0-1-Sequence
Bit Pattern for SYNC
0 1 0 1 0 1 . . .
. . . 0 1 0 1 0 1
Data Packet
W
0
. . . W
15
SYNC
0-1-Sequence
12.28 ms
13.81 ms
Figure 2:
Transmission protocol of the ASCell3911.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ASCELL3912 | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter |
| ASCF21U | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:CERAMIC SURFACE-MOUNT 21.4MHz and 45MHz FUNDAMENTAL MONOLITHIC CRYSTAL FILTERS |
| ASCF21U15 | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:CERAMIC SURFACE-MOUNT 21.4MHz and 45MHz FUNDAMENTAL MONOLITHIC CRYSTAL FILTERS |
| ASCF21U20 | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:CERAMIC SURFACE-MOUNT 21.4MHz and 45MHz FUNDAMENTAL MONOLITHIC CRYSTAL FILTERS |
| ASCF21U30 | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:CERAMIC SURFACE-MOUNT 21.4MHz and 45MHz FUNDAMENTAL MONOLITHIC CRYSTAL FILTERS |
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