參數(shù)資料
型號: ASCELL3911
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ER 6C 6#16 SKT RECP LINE
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO14
封裝: TSSOP-14
文件頁數(shù): 12/13頁
文件大?。?/td> 104K
代理商: ASCELL3911
ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet
ASCell3911
Rev. A, February 2000
Page 12 of 13
Austria Mikro Systeme International AG
Pin
Name
Type
Description
4
RESET /
TEST
O
Power-On-Reset output
Test output in test mode
5
XTAL
A
XTAL oscillator input
6
VDDSYN
P
PLL, mixer positive supply
7
GNDSYN
P
PLL, mixer, negative supply
8
GND
P
Negative supply of DC/DC, POR, LBAT, XOSC, Data Interface, SinCos
9
uC_CLK
O
Clock output for micro-controller
10
WAKEUP
I
Wake-up signal, pos. edge wakes up the chip, negative edge stops transmis-
sion
11
D_CLK
I
Data clock, data is clocked into the chip with negative edge of DCLK
12
D_EN
I
Data enable, high while data is clocked into the chip
13
DATA
I
Data input for 128 bits of FSK data preceeded by 8 control bits
14
VDD
P
Positive supply of DC/DC, POR, LBAT, XOSC, Data Interface, SinCos
4
Application Schematic
DC to 80 kHz
RF_LO = f
R F
f =868.300 MHz
R
F
G. Schultes, ISM868_TX
Revision: 0, 99 07 16
f/64
+/-45°
Protocol
Encoder
Transmit.
Timing
Driving
Amplifier.
90°
Sin / Cos
Generator
Baseband
Filters
Loop-filter
GNDSYN
VDDSYN
VDDSYN
XTAL
Phase Detector
XTAL
Oscillator
Local
Oscillator
Quadrature
Up Converter
WAKEUP
DATA
D_EN
D_CLK
μC_CLK
Reset/Test
DRA
QUC
2*BBF
XTO
VCO
LPF
DIV PHD
SCG
C
PAGND
RF-
RF+
DVCC
DGND
DVCC
DGND
GNDSYN
Implementation
Example
Figure 6: Basic application schematic of the ASCell3911.
相關(guān)PDF資料
PDF描述
ASCELL3912 ER 10C 10#16 SKT RECP LINE
ASD07H-12D12 Isolated and Regulated 7 WATT Open Frame DC/DC Converter
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