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參數(shù)資料
| 型號： | ASCELL3911 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ER 6C 6#16 SKT RECP LINE |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 104K |
| 代理商： | ASCELL3911 |
ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet
ASCell3911
Rev. A, February 2000
Page 10 of 13
Austria Mikro Systeme International AG
2.3
TA = 23 °C, VDD, VSYN = 2,7 V, unless specified otherwise. Device functional for TA= -40 to
+85 °C.
FSK Operation
Symbol
Parameter
Conditions / Notes
Min
Typ
Max
Units
F
C
Carrier frequency
Depends on different external
crystals.
315,000
433,920
868,300
MHz
MHz
MHz
F
FSK frequency deviation 315,000 MHz:
433,920 MHz:
868,300 MHz:
-68,4
-61,7
-61,7
+68,4
+61,7
+61,7
kHz
kHz
kHz
F
xosc
Crystal oscillator (XOSC)
frequency
315,000 MHz, Crystal=H
433,920 MHz, Crystal=L
868,300 MHz, Crystal=L
19,6875
13,5600
13,5672
MHz
MHz
MHz
FT
xosc
Crystal oscillator (XOSC)
fequency tolerance
315,000 M: (-40~+85 °C),
433,920 MHz: (-40~+85 °C),
868,300 MHz: (-40~+85 °C)
50
50
25
ppm
ppm
ppm
D
R,gross
P
out
Gross data rate
Including burst protocol.
18,235
1)
kbps
Available output power,
into Z
out
= 2000
differ-
ential
315,000MHz (USA),
433,920 MHz
868,300 MHz
315MHz (Japan) - set through
RPA
-1,5
–1,5
–3,0
0,0
0,0
-1,5
-20
+1,5
+1,5
+0,0
dBm
dBm
dBm
dBm
T
abTX
Time between two differ-
ent transmitted mes-
sages “a”&“b”
1)
@ 868,300 MHz: D
R,gross
= 13,5672 MHz / 46,5 / 16 = 18,235 kbps.
@ 433,920 MHz: 18,225 kbps.
@ 315,000 MHz: 19,226 kbps.
2)
Antenna dependent - will not be production tested.
30
ms
2.4
TA = 23 °C, VDD = 2,7 V, unless specified otherwise. GND is the 0 V reference.
Input parameters for bi-directional pins (μC_CLK, WAKEUP) are valid at disabled outputs.
Digital Pin Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
μC_CLK (μC clock output / wake-up input)
VOH
High level output voltage
IOH =-1 mA
VDD-0,5
-
V
VOL
Low level output voltage
IOL =1 mA
-
0,3
V
tr
Rise time
CLoad = 10 pF
20
ns
td
Fall time
CLoad = 10 pF
20
ns
jcc
Cycle to cycle jitter
+/-5
%
VIH
High level input voltage
VDD-0,5
-
V
VIL
Low level input voltage
-
0,3
V
IIH
High level input current
VIH = VDD
1
μA
IIL
Low level input current
VIL =0 V; Due to in-
ternal pull-up
-40
μA
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