參數(shù)資料
型號(hào)： AS9C25128M2036L-166FC
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
中文描述： 128K X 36 DUAL-PORT SRAM, 10 ns, PBGA208
封裝： FBGA-208
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 1109K
代理商： AS9C25128M2036L-166FC
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3
Alliance Semiconductor
P. 7 of 30
Signal description
Signal
Port A
Notes:
1. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
2. OPT
x
,VDDQ
x
and VDD must be set to appropriate operating levels before applying inputs on the I/Os and controls for that port.
3. OPT
x
= VDD (2.5V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 3.3V level and VDDQ
x
must be supplied at 3.3V.
OPT
x
= VSS (0V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 2.5V level and VDDQ
x
must be supplied at 2.5V.
Each port can independently operate on either of the VDDQ levels.
4. If unused JTAG inputs may be left unconnected.
5. JTAG is not supported in PQFP package.
6. Address A17 is a NC forAS9C25128M2036L
I/O Properties
Description
Notes
Port B
CLK
A
CLK
B
I
CLOCK
Clock. Each port has an independent Clock input that can be of different frequencies.
All inputs except
OE
x
and ZZ
x
are synchronous to the corresponding port’s clock and
must meet setup and hold time about the rising edge of the clock.
External Address. Sampled on the rising edge of corresponding port clock
Bidirectional data pins
Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of
corresponding port clock.
Read/Write enable. Drive this pin LOW to write to, or HIGH to Read from the
memory array.
Byte Enable Inputs. Active low. Asserting these signals enables Read and Write
operations to the corresponding bytes of the memory array. (Refer Byte Control
Truth Table)
Address Strobe Enable.Active low. Loads external address onto the counter. (Refer
Counter Control Truth Table)
Address Counter Increment. Active low. Increments the counter value. (Refer
Counter Control Truth Table)
Address Counter Repeat. Active low. Reloads the counter with the previously loaded
external address.(Refer Counter Control Truth Table)
Asynchronous output enable. I/O pins are driven when the
OE
is low and the chip is
in Read mode. A high on
OE
tristates the I/O pins.
Snooze Mode Input. Places the device in low power mode. Data is retained. This pin
has an internal pull-down and can be floating.
Pipeline/Flow-Through Select. When low, enables single register flow-through
mode. When high, enables double register Pipeline mode. This pin has an internal
pull-up and can be left floating to operate in pipeline mode.
VDDQ
x
Option. OPT
x
selects the operating voltage levels for the I/Os, addresses,
clock, and controls on that port. This pin has an internal pull-up and can be left
floating to operate in 3.3V mode.
Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic
Truth Table)
Collision Alert Flag. Used to indicate collision during simultaneous memory access
to the same location by both the ports (Refer Collision Detection Truth Table)
Power to I/O bus. Can be 3.3V or 2.5V depending on OPT
x
input.
Power Inputs (To be connected to 2.5V Power supply)
GROUND
Ground Inputs (To be connected to Ground supply)
CLOCK
(JTAG)
SYNC
(JTAG)
registers.
SYNC
(JTAG)
normally tristated except when the captured data is shifted out of the JTAG TAP.
SYNC
(JTAG)
machine transitions occur on the rising edge of TCK.
ASYNC
(JTAG)
1
A0
A
- A17
A
DQ0
A
- DQ35
A
DQ0
B
- DQ35
B
I/O
A0
B
- A17
B
I
SYNC
SYNC
6
CE0
A
, CE1
A
CE0
B
, CE1
B
I
SYNC
R/W
A
R/W
B
I
SYNC
BE0
A
- BE3
A
BE0
B
- BE3
B
I
SYNC
ADS
A
ADS
B
I
SYNC
INC
A
INC
B
I
SYNC
RPT
A
RPT
B
I
SYNC
OE
A
OE
B
I
ASYNC
ZZ
A
ZZ
B
I
ASYNC
PL/FT
A
PL/FT
B
I
STATIC
OPT
A
OPT
B
I
STATIC
1,2,3
INT
A
INT
B
O
SYNC
COL
A
COL
B
O
SYNC
VDDQ
A
VDDQ
B
I
I
I
POWER
POWER
1,2,3
2
VDD
VSS
TCK
I
JTAG Test Clock Input. All JTAG signals except
TRST
are synchronous to this clock.
4,5
TDI
I
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
4,5
TDO
O
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
5
TMS
I
JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State
4,5
TRST
I
JTAG Test Reset Input. Asynchronous input used to initialize TAP controller.
4,5
相關(guān)PDF資料
PDF描述
AS9C25256M2036L-166FI IC REG LDO 1.5A 1.5V TO-252
AS9C25128M2036L-166FI IC REG LDO 1.5A 1.8V TO-252
AS9C25256M2036L-166PC IC REG LDO 1.5A 2.5V TO-252
AS9C25128M2036L-166PC IC REG LDO 1.5A 3.3V TO-252
AS9C25256M2036L-166PI IC REG LDO 1.5A POS ADJ TO-252
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS9C25128M2036L-166FI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-166PC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-166PI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-200BC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-200BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
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