參數(shù)資料
型號(hào)： AS9C25128M2036L-166FC
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
中文描述： 128K X 36 DUAL-PORT SRAM, 10 ns, PBGA208
封裝： FBGA-208
文件頁(yè)數(shù)： 16/30頁(yè)
文件大小： 1109K
代理商： AS9C25128M2036L-166FC
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3
Alliance Semiconductor
P. 16 of 30
Mailbox Interrupts
The AS9C25256M2036L/AS9C25128M2036L has an Inbuilt Mailbox Logic that can be used for communication between the two ports.
One memory location is assigned as mail box (message center) for each port. The location 3FFFE (HEX) is assigned as the message center
for Port A and 3FFFF (HEX) for Port B (IFFFE and IFFFF for AS9C25128M2036L). The port A interrupt flag (INT
A
) is asserted when the
port B writes to memory location 3FFFE (HEX) (IFFFE for AS9C25128M2036L). The port A clears the interrupt flag by reading the address
location 3FFFE (HEX) (IFFFE for AS9C25128M2036L). Likewise, the port B interrupt flag (INT
B
) is asserted when the port A writes to
memory location 3FFFF (HEX)(IFFFF for AS9C25128M2036L) and to clear the interrupt flag (INT
B
), the port B must read the memory
location 3FFFF (IFFFF for AS9C25128M2036L) (Refer Interrupt Logic Truth Table).
The interrupt flag is asserted in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-
through mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without de-asserting the
interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT
pins can be ignored.
Interrupt logic truth table
[1,4]
Notes:
1. L = low, H = high, X = don't care
2. CE
x
is an internal signal ('x' = 'A' or 'B'). CE
x
= H implies 'Chip is Deselected' (CE0
x
= H or CE1
x
=L), CE
x
= L implies 'Chip is Selected' (CE0
x
= L and CE1
x
=H)
3. Address specified here is the internal address (refer Counter control truth table).
4. Both Interrupt Flags are De-asserted on power-up.
5. Address A17 is a NC for AS9C25128M2036L, hence Interrupt addresses are IFFFF and IFFFE
CLK
A
R/W
A
CE
A[2]
A17
A
-A0
A[3,5]
L to H
L
L
L to H
X
X
L to H
X
X
L to H
H
L
CLK
B
L to H
L to H
L to H
L to H
R/W
B
X
H
L
X
CE
B[2]
A17
B
-A0
B[3,5]
X
L
L
X
INT
A
X
X
L
H
INT
B
L
H
X
X
Function
3FFFF
X
X
3FFFE
X
Assert Port B Interrupt Flag
De-assert Port B Interrupt Flag
Assert Port A Interrupt Flag
De-assert Port A Interrupt Flag
3FFFF
3FFFE
X
相關(guān)PDF資料
PDF描述
AS9C25256M2036L-166FI IC REG LDO 1.5A 1.5V TO-252
AS9C25128M2036L-166FI IC REG LDO 1.5A 1.8V TO-252
AS9C25256M2036L-166PC IC REG LDO 1.5A 2.5V TO-252
AS9C25128M2036L-166PC IC REG LDO 1.5A 3.3V TO-252
AS9C25256M2036L-166PI IC REG LDO 1.5A POS ADJ TO-252
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS9C25128M2036L-166FI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-166PC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-166PI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-200BC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25128M2036L-200BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
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