參數(shù)資料
型號: AS80C51-36R
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQCC44
文件頁數(shù): 94/170頁
文件大?。?/td> 4133K
代理商: AS80C51-36R
3
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
2.
Overview
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architec-
ture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs
approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing
speed.
Figure 2-1.
Block Diagram
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code effi-
cient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of
SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM
STACK
POINTER
SRAM
PROGRAM
COUNTER
PROGRAMMING
LOGIC
ISP
INTERFACE
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
RESET FLAG
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
INTERRUPT
UNIT
ANALOG
COMPARATOR
ADC
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
VCC
RESET
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
DRIVERS
PORT B
GND
PB3:0
8-BIT DATA BUS
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