參數(shù)資料
型號(hào)： AS80196CA
廠商： Intel Corp.
英文描述： ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0
中文描述： 先進(jìn)的16位單片機(jī)CHMOS集成CAN 2.0
文件頁數(shù)： 8/33頁
文件大?。?/td> 453K
代理商： AS80196CA
87C196CA/87C196CB
Symbol
Name and Function
P5.7/BUSWIDTH
(CB only)
Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dynamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low,
an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ‘‘0’’
and CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is
‘‘0’’, all bus cycles are 16-bit. CCR bit 1
e
‘‘0’’ and CCR1 bit 2
e
‘‘0’’ is illegal. Also
an LSIO pin when not used as BUSWIDTH.
P5.6/READY
Ready input to lengthen external memory cycles, for interfacing with slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller
goes into a wait state mode until the next opositive transition in CLKOUT occurs with
READY high. When external memory is not used, READY has no effect. The max
number of wait states inserted into the bus cycle is controlled by the CCR/CCR1.
Also an LSIO if READY is not selected.
P5.5/BHE
Y
/WRH
Y
Byte High Enable or Write High output, as selected by the CCR. BHE
Y
e
0 selects
the bank of memory that is connected to the high byte of the data bus. A0
e
0
selects the bank of memory that is connected to the low byte. Thus accesses to a
16-bit wide memory can be to the low byte only (A0
e
0, BHE
Y
e
1), to the high
byte only (A0
e
1, BHE
Y
e
0) or both bytes (A0
e
0, BHE
Y
e
0). If the WRH
Y
function is selected, the pin will go low if the bus cycle is writing to an odd memory
location. BHE
Y
/WRH
Y
is only valid during 16-bit external. Also an LSIO pin when
not BHE/WRH
Y
.
P5.4/SLPINT
Dual function I/O pin. As a bidirectional port pin or as a system function. The system
function is a Slave Port Interrupt Output Pin (on CA, bidirectional port pin only).
P5.3/RD
Y
Read signal output to external memory. RD
Y
is active only during external memory
reads or LSIO when not used as RD
Y
.
P5.2/WR
Y
/WRL
Y
Write and Write Low output to external memory, as selected by the CCR, WR
Y
will
go low for every external write, while WRL
Y
will go low only for external writes where
an even byte is being written. WR
Y
/WRL
Y
is active during external memory writes.
Also an LSIO pin when not used as WR
Y
/WRL
Y
.
P5.1/INST
(CB only)
Output high during an external memory read indicates the read is an instruction
fetch. INST is valid throughout the bus cycle. INST is active only during external
memory fetches, during internal EPROM fetches INST is held low. Also LSIO when
not INST.
P5.0/ALE/ADV
Y
Address Latch Enable or Address Valid Output, as selected by CCR. Both pin
options provide a latch to demultiplex the address from the address/data bus. When
the pin is ADV
Y
, it goes inactive (high) at the end of the bus cycle. ADV
Y
can be
used as a chip select for external memory. ALE/ADV
Y
is active only during external
memory accesses. Also LSIO when not used as ALE.
8
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參數(shù)描述
AS80196CB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0
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