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參數(shù)資料
| 型號： | AS80196CA |
| 廠商： | Intel Corp. |
| 英文描述： | ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 |
| 中文描述： | 先進(jìn)的16位單片機(jī)CHMOS集成CAN 2.0 |
| 文件頁數(shù)： | 23/33頁 |
| 文件大小： | 453K |
| 代理商： | AS80196CA |
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87C196CA/87C196CB
t
e
1 state time (125 ns
@
16 MHz)
NORMAL MASTER/SLAVE OPERATION
Symbol
Parameter
Min
Max
Units
T
CHCH
Clock Period
4t
ns
T
CLCH
Clock Low Time/Clock High Time
2t
b
10
ns
(1)
T
CLDV
Clock Falling to Data Out Valid (Master)
0.5t
1.5t
a
20
ns
T
CLDV1
Clock Falling to Data Out Valid (Slave)
0.5t
1.5t
a
50
ns
T
DVCH
Data In Setup to Clock Rising Edge
10
ns
T
CHDX
Clock Rising Edge to Data in Invalid
t
a
15
ns
*
Timings are guaranteed by design.
HANDSHAKE OPERATION
Symbol
Parameter
Min
Max
Units
T
CHCH
Clock Period
4t
ns
T
CLCH
Clock Low Time/Clock High Time
2t
b
10
ns
(1)
T
CLDV
Clock Falling to Data Out Valid (Master)
0.5t
1.5t
a
20
ns
T
CLDV1
Clock Falling to Data Out Valid (Slave)
0.5t
1.5t
a
50
ns
T
DVCH
Data In Setup to Clock Rising Edge
10
ns
T
CLDX
Clock Rising Edge to Data in Invalid
t
a
15
ns
*
Timings are guaranteed by design.
NOTE:
1. This specification refers to input clocks during slave operation. During master operation, the device will output a nominal
50% duty cycle clock.
272405–34
NOTE:
The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active-high clock signal.
The SCx signal will be different for other configurations, however, setup and hold timings will still be the same in relation
to the latching edge of SCx.
Figure 6. Synchronous Serial Port
23
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| AS80196CB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 |
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