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參數(shù)資料
| 型號： | AS80196CA |
| 廠商： | Intel Corp. |
| 英文描述： | ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 |
| 中文描述： | 先進的16位單片機CHMOS集成CAN 2.0 |
| 文件頁數(shù)： | 16/33頁 |
| 文件大?。?/td> | 453K |
| 代理商： | AS80196CA |
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87C196CA/87C196CB
AC CHARACTERISTICS
(Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins
e
100 pF, Rise and Fall Times
e
10 ns.
The 87C196CA/CB will meet these specifications
Symbol
Parameter
Min
Max
Units
F
XTAL
Frequency on XTAL1
4.0
20
MHz
(1)
T
OSC
XTAL1 Period (1/F
XTAL
)
50.0
250
ns
T
XHCH
XTAL1 High to CLKOUT High or Low
a
20
110
ns
T
OFD
Clock Failure to Reset Pulled Low
(6)
4
40
m
s
T
CLCL
CLKOUT Period
2 T
OSC
ns
T
CHCL
CLKOUT High Period
T
OSC
b
10
T
OSC
a
15
ns
T
CLLH
CLKOUT Low to ALE/ADV High
b
15
a
10
ns
T
LLCH
ALE/ADV Low to CLKOUT High
b
20
a
15
ns
T
LHLH
ALE/ADV Cycle Time
4 T
OSC
ns
(5)
T
LHLL
ALE/ADV High Time
T
OSC
b
10
T
OSC
a
10
ns
T
AVLL
Address Valid to ALE Low
T
OSC
b
15
ns
T
LLAX
Address Hold After ALE/ADV Low
T
OSC
b
40
ns
T
LLRL
ALE/ADV Low to RD Low
T
OSC
b
30
ns
T
RLCL
RD Low to CLKOUT Low
CA
CB
a
4
b
8
a
30
a
20
ns
ns
T
RLRH
RD Low Period
T
OSC
b
10
ns
(5)
T
RHLH
RD High to ALE/ADV High
T
OSC
T
OSC
a
25
ns
(3)
T
RLAZ
RD Low to Address Float
5
ns
T
LLWL
ALE/ADV Low to WR Low
T
OSC
b
10
ns
T
CLWL
CLKOUT Low to WR Low
b
5
a
25
ns
T
QVWH
Data Valid before WR High
T
OSC
b
23
ns
T
CHWH
CLKOUT High to WR High
b
10
a
15
ns
T
WLWH
WR Low Period
CB
CA
T
OSC
b
30
T
OSC
b
20
ns
(5)
T
WHQX
Data Hold after WR High
T
OSC
b
25
ns
T
WHLH
WR High to ALE/ADV High
T
OSC
b
10
T
OSC
a
15
ns
(3)
T
WHBX
BHE, INST Hold after WR High
T
OSC
b
10
ns
T
WHAX
AD8–15 Hold after WR High
T
OSC
b
30
ns
(4)
T
RHBX
BHE, INST Hold after RD High
T
OSC
b
10
ns
T
RHAX
AD8–15 Hold after RD High
T
OSC
b
30
ns
(4)
NOTES:
1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 Tosc
c
n, where n
e
number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 T
OSC
to specification.
6. T
OFD
is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H. Programming the CDE bit enables oscillator fail detec-
tion.
16
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