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參數(shù)資料
| 型號： | AS7C33512PFS16A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 512K×16 Pipeline Burst Synchronous SRAM(3.3V 512K×16流水線脈沖同步靜態(tài)RAM) |
| 中文描述： | 3.3為512k × 16管道爆裂同步SRAM的電壓（3.3V為512k × 16流水線脈沖同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 215K |
| 代理商： | AS7C33512PFS16A |
AS7C33512PFS16A
AS7C33512PFS18A
3/13/01
;
v.0.9
Alliance Semiconductor
6
Timing characteristics over operating range
*“Notes” column refers to “notes” on page 10.
Key to switching waveforms
Parameter
Symbol
–166
–150
–133
–100
Unit
Notes*
Min
Max
Min
Max
Min
Max
Min
Max
Clock frequency
f
Max
t
CYC
t
CYCF
t
CD
–
166
–
150
–
133
–
100
MHz
Cycle time (pipelined mode)
6
–
6.6
–
7.5
–
10
–
ns
Cycle time (flow-through mode)
10
–
10
–
12
–
12
–
ns
Clock access time (pipelined mode)
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock access time (flow-through
mode)
t
CDF
–
9
–
10
–
10
–
12
ns
Output enable LOW to data valid
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock HIGH to output Low Z
0
–
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
–
3.5
–
3.8
–
4.0
–
4.5
ns
2,3,4
Clock HIGH to output High Z
–
3.5
–
3.8
–
4.0
–
5.0
ns
2,3,4
Output enable HIGH to invalid output
0
–
0
–
0
–
0
–
ns
Clock HIGH pulse width
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Clock LOW pulse width
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Address setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Data setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Write setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,8
Address hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSP setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSC setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADV hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold fromclock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Undefined/don’t care
Falling input
Rising input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512PFS18A | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQC | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQCN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQI | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQIN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512PFS18A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
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