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參數資料
| 型號： | AS7C33512PFS16A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 512K×16 Pipeline Burst Synchronous SRAM(3.3V 512K×16流水線脈沖同步靜態(tài)RAM) |
| 中文描述： | 3.3為512k × 16管道爆裂同步SRAM的電壓（3.3V為512k × 16流水線脈沖同步靜態(tài)內存） |
| 文件頁數： | 3/11頁 |
| 文件大?。?/td> | 215K |
| 代理商： | AS7C33512PFS16A |
AS7C33512PFS16A
AS7C33512PFS18A
3/13/01
;
v.0.9
Alliance Semiconductor
3
Signal descriptions
Signal
Absolute maximum ratings
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
I/O
Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE,
FT
, ZZ,
LBO
are synchronous to this clock.
A0–A18
I
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When
CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active HIGH and active LOW respectively. Sampled on
clock edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe (processor). Asserted LOW to load a new address or to enter
standby mode.
ADSC
I
SYNC
Address strobe (controller). Asserted LOW to load a new address or to enter
standby mode.
ADV
I
SYNC
Burst advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and
BW[a,b] control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]
inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and
BWE = LOW If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the
cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is
in read mode.
LBO
I
STATIC default =
HIGH
Count mode. When driven HIGH, count sequence follows Intel XOR convention.
When driven LOW count sequence follows linear convention. This signal is
internally pulled HIGH.
FT
I
STATIC
Flow-through mode.When LOW enables single register flow-through mode.
Connect to V
DD
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if
unused.
ZZ
I
ASYNC
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
–0.5
+4.6
V
Input voltage relative to GND (input pins)
–0.5
V
DD
+ 0.5
V
DDQ
+ 0.5
1.8
V
Input voltage relative to GND (I/O pins)
–0.5
V
Power dissipation
–
W
DC output current
–
50
mA
°
C
°
C
Storage temperature (plastic)
–65
+150
Temperature under bias
–65
+135
相關PDF資料 |
PDF描述 |
|---|---|
| AS7C33512PFS18A | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQC | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQCN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQI | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQIN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AS7C33512PFS18A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
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