- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381343 > AS7C33512NTD18A-166TQI (ALLIANCE SEMICONDUCTOR CORP) 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD PDF資料下載
參數(shù)資料
| 型號(hào)： | AS7C33512NTD18A-166TQI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| 中文描述： | 512K X 18 ZBT SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 9/19頁(yè) |
| 文件大?。?/td> | 439K |
| 代理商： | AS7C33512NTD18A-166TQI |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
AS7C33512NTD18A
11/30/04;
v.2.1
Alliance Semiconductor
9 of 19
Timing characteristics over operating range for 3.3V I/O
Parameter
Symbol
–166
–133
Unit
Notes
1
1 Refer to “notes” on page 16.
Min
–
6
Max
166
–
Min
–
7.5
Max
133
–
Clock frequency
f
Max
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
CENS
t
CENH
t
ADVS
t
ADVH
MHz
ns
Cycle time
Clock access time
–
3.5
–
4.0
ns
Output enable LOW to data valid
–
0
3.5
–
–
0
4.0
–
ns
ns
Clock HIGH to output Low Z
2,3,4
Data output invalid from clock HIGH
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
–
–
3.5
3.5
–
–
4.0
4.0
ns
ns
2,3,4
2,3,4
Clock HIGH to output High Z
Output enable HIGH to invalid output
0
–
0
–
ns
Clock HIGH pulse width
2.4
2.4
–
–
2.5
2.5
–
–
ns
ns
5
5
Clock LOW pulse width
Address setup to clock HIGH
1.5
–
1.5
–
ns
6
Data setup to clock HIGH
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6
Write setup to clock HIGH
6,7
Chip select setup to clock HIGH
1.5
–
1.5
–
ns
6,8
Address hold from clock HIGH
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6
6
Data hold from clock HIGH
Write hold from clock HIGH
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
0.5
1.5
–
–
0.5
1.5
–
–
ns
ns
6,8
6
Clock enable
setup to clock HIGH
Clock enable hold from clock HIGH
0.5
–
0.5
–
ns
6
ADV/LD
setup to clock HIGH
1.5
0.5
–
–
1.5
0.5
–
–
ns
ns
6
6
ADV/LD
hold from clock HIGH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512NTD18A-166TQIN | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQCN | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQI | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512NTD18A-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。