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參數(shù)資料
| 型號： | AS7C33512NTD18A-166TQI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| 中文描述： | 512K X 18 ZBT SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 439K |
| 代理商： | AS7C33512NTD18A-166TQI |
11/30/04;
v.2.1
Alliance Semiconductor
10 of 19
AS7C33512NTD18A
Snooze Mode Electrical Characteristics
Timing characteristics over operating range for 2.5 V I/O
Parameter
Symbol
–166
–133
Unit
Notes
1
1 Refer to “notes” onpage 16.
Min
Max
Min
Max
Clock frequency
f
Max
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
CENS
t
CENH
t
ADVS
t
ADVH
–
166
–
133
MHz
Cycle time
6
–
–
7.5
–
–
ns
ns
Clock access time
4.0
4.5
Output enable low to data valid
–
3.5
–
4.0
ns
Clock high to output low Z
0
–
–
0
–
–
ns
ns
2,3,4
2
Data output invalid from clock high
1.5
1.5
Output enable low to output low Z
0
–
0
–
ns
2,3,4
Output enable high to output High Z
–
–
3.5
3.5
–
–
4.0
4.0
ns
ns
2,3,4
2,3,4
Clock high to output High Z
Output enable high to invalid output
0
–
0
–
ns
Clock high pulse width
2.4
2.3
–
–
2.5
2.5
–
–
ns
ns
5
5
Clock low pulse width
Address setup to clock high
1.7
–
1.7
–
ns
6
Data setup to clock high
1.7
1.7
–
–
1.7
1.7
–
–
ns
ns
6
Write setup to clock high
6,7
Chip select setup to clock high
1.7
–
1.7
–
ns
6,8
Address hold from clock high
0.7
0.7
–
–
0.7
0.7
–
–
ns
ns
6
6
Data hold from clock high
Write hold from clock high
0.7
–
0.7
–
ns
6,7
Chip select hold from clock high
0.7
1.7
–
–
0.7
1.7
–
–
ns
ns
6,8
6
Clock enable
setup to clock high
Clock enable hold from clock high
0.7
–
0.7
–
ns
6
ADV/LD
setup to clock high
1.7
–
1.7
–
ns
6
ADV/LD
hold from clock high
0.7
–
0.7
–
ns
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
30
Units
mA
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512NTD18A-166TQIN | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQCN | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQI | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512NTD18A-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
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