- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381343 > AS7C33512NTD18A-166TQI (ALLIANCE SEMICONDUCTOR CORP) 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD PDF資料下載
參數(shù)資料
| 型號(hào)： | AS7C33512NTD18A-166TQI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| 中文描述： | 512K X 18 ZBT SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 4/19頁(yè) |
| 文件大?。?/td> | 439K |
| 代理商： | AS7C33512NTD18A-166TQI |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
11/30/04;
v.2.1
Alliance Semiconductor
4 of 19
AS7C33512NTD18A
Functional description
The AS7C33512NTD18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM)
organized as 524,288 words × 18 bits and incorporates a LATE LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD
) architecture, featuring an enhanced
write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce
overall bandwidth for applications requiring random access or read-modify-write operations.
NTD
devices use the memory bus more efficiently by introducing a write 'latency' which matches the two cycle pipeline and
one cycle flowthrough read latency. Write data is applied two cycles after the write command and address, allowing the read
pipeline to clear. With NTD
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W LOW to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied LOW for
full 18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is
applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled
for write operations; it can be tied LOW for normal operations. Outputs go to a high impedance state when the device is de-
selected by any of the three chip enable inputs (refer to synchronous truth table on page page 6.) In pipeline mode, a two cycle
deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is HIGH, external
addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the
LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD18A operate with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate
power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP.
*Guaranteed not tested
TQFP thermal resistance
Capacitance
Parameter
Symbol
C
IN*
C
I/O*
Signals
Test conditions
Max
Unit
Input capacitance
Address and control pins
V
IN
= 0V
V
IN
= V
OUT
= 0V
5
pF
I/O capacitance
I/O pins
7
pF
Description
Conditions
Symbol
θ
JA
θ
JA
Typical
40
22
Units
°
C/W
°
C/W
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
4–layer
θ
JC
8
°
C/W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512NTD18A-166TQIN | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQCN | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQI | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512NTD18A-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。