參數(shù)資料
型號(hào): AS7C33256PFS36A-133TQCN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 256K x 32/36 pipelined burst synchronous SRAM
中文描述: 256K X 36 STANDARD SRAM, 10 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 17/20頁
文件大?。?/td> 527K
代理商: AS7C33256PFS36A-133TQCN
AS7C33256PFS32A
AS7C33256PFS36A
11/30/04, v.3.1
Alliance Semiconductor
P. 17 of 20
AC test conditions
Output load: see Figure B, except for t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C.
Notes
1
2
3
4
5
6
For test conditions, see
AC Test Conditions
, Figures A, B, and C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given temperature and voltage.
tCH measured as high above V
IH
, and tCL measured as low below V
IL
.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to
GWE
,
BWE
, and
BW[a:d].
Chip select refers to
CE0
,
CE1
, and
CE2
.
7
8
353
/ 1538
5 pF*
319
/ 1667
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Z
0
= 50
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
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AS7C33256PFS36A-133TQI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM
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