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參數(shù)資料
| 型號： | AS7C33256PFS36A-133TQCN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| 中文描述： | 256K X 36 STANDARD SRAM, 10 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 527K |
| 代理商： | AS7C33256PFS36A-133TQCN |
AS7C33256PFS32A
AS7C33256PFS36A
11/30/04, v.3.1
Alliance Semiconductor
P. 10 of 20
Timing characteristics for 3.3 V I/O operation
Parameter
Symbol
–166
–133
Unit
Notes
1
Min
Max
Min
Max
Clock frequency
Cycle time
f
Max
t
CYC
–
6
166
–
–
133
–
MHz
ns
7.5
Clock access time
t
CD
-
3.5
-
4.0
ns
Output enable low to data valid
Clock high to output low Z
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–
0
3.5
–
–
0
4.0
–
ns
ns
2,3,4
Data output invalid from clock high
1.5
–
1.5
–
ns
2
Output enable low to output low Z
Output enable high to output high Z
0
–
–
0
–
–
ns
ns
2,3,4
2,3,4
3.5
4.0
Clock high to output high Z
–
3.5
–
4.0
ns
2,3,4
Output enable high to invalid output
Clock high pulse width
0
–
–
0
–
–
ns
ns
2.4
2.5
5
Clock low pulse width
2.3
–
2.5
–
ns
5
Address setup to clock high
Data setup to clock high
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6
6
Write setup to clock high
1.5
–
1.5
–
ns
6,7
Chip select setup to clock high
Address hold from clock high
1.5
0.5
–
–
1.5
0.5
–
–
ns
ns
6,8
6
Data hold from clock high
0.5
–
0.5
–
ns
6
Write hold from clock high
Chip select hold from clock high
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6,7
6,8
ADV setup to clock high
1.5
–
1.5
–
ns
6
ADSP setup to clock high
1.5
–
1.5
–
ns
6
ADSC setup to clock high
ADV hold from clock high
1.5
0.5
–
–
1.5
0.5
–
–
ns
ns
6
6
ADSP hold from clock high
0.5
–
0.5
–
ns
6
ADSC hold from clock high
0.5
–
0.5
–
ns
6
1
See “Notes” on page 17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33256PFS36A-133TQI | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C332MFT18A-10TQI | 3.3V 2M x 18 Flow-through synchronous SRAM |
| AS7C332MFT18A-10TQIN | 3.3V 2M x 18 Flow-through synchronous SRAM |
| AS7C332MFT18A-75TQC | 3.3V 2M x 18 Flow-through synchronous SRAM |
| AS7C332MFT18A-75TQCN | 3.3V 2M x 18 Flow-through synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33256PFS36A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-166TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-166TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
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