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參數(shù)資料
| 型號(hào)： | AS7C33256PFS36A-133TQCN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| 中文描述： | 256K X 36 STANDARD SRAM, 10 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大小： | 527K |
| 代理商： | AS7C33256PFS36A-133TQCN |
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AS7C33256PFS32A
AS7C33256PFS36A
11/30/04, v.3.1
Alliance Semiconductor
P. 11 of 20
Snooze Mode Electrical Characteristics
Timing characteristics for 2.5 V I/O operation
Parameter
Symbol
f
Max
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–166
–133
Unit
MHz
Notes
1
Min
–
Max
166
Min
–
Max
133
Clock frequency
Cycle time
6
–
7.5
–
ns
Clock access time
Output enable low to data valid
-
–
3.8
3.5
-
–
4.2
4.0
ns
ns
Clock high to output low Z
0
–
0
–
ns
2,3,4
Data output invalid from clock high
Output enable low to output low Z
1.5
0
–
–
1.5
0
–
–
ns
ns
2
2,3,4
Output enable high to output high Z
–
3.5
–
4.0
ns
2,3,4
Clock high to output high Z
Output enable high to invalid output
–
0
3.5
–
–
0
4.0
–
ns
ns
2,3,4
Clock high pulse width
2.4
–
2.5
–
ns
5
Clock low pulse width
Address setup to clock high
2.3
1.7
–
–
2.5
1.7
–
–
ns
ns
5
6
Data setup to clock high
1.7
–
1.7
–
ns
6
Write setup to clock high
Chip select setup to clock high
1.7
1.7
–
–
1.7
1.7
–
–
ns
ns
6,7
6,8
Address hold from clock high
0.7
–
0.7
–
ns
6
Data hold from clock high
Write hold from clock high
0.7
0.7
–
–
0.7
0.7
–
–
ns
ns
6
6,7
Chip select hold from clock high
0.7
–
0.7
–
ns
6,8
ADV setup to clock high
ADSP setup to clock high
1.7
1.7
–
–
1.7
1.7
–
–
ns
ns
6
6
ADSC setup to clock high
1.7
–
1.7
–
ns
6
ADV hold from clock high
ADSP hold from clock high
0.7
0.7
–
–
0.7
0.7
–
–
ns
ns
6
6
ADSC hold from clock high
0.7
–
0.7
–
ns
6
1
See “Notes” on page 17
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
30
Units
mA
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33256PFS36A-133TQI | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C332MFT18A-10TQI | 3.3V 2M x 18 Flow-through synchronous SRAM |
| AS7C332MFT18A-10TQIN | 3.3V 2M x 18 Flow-through synchronous SRAM |
| AS7C332MFT18A-75TQC | 3.3V 2M x 18 Flow-through synchronous SRAM |
| AS7C332MFT18A-75TQCN | 3.3V 2M x 18 Flow-through synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33256PFS36A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-166TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS36A-166TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
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