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參數(shù)資料
| 型號(hào)： | AS7C33256NTF32A-75TQCN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| 中文描述： | 256K X 32 ZBT SRAM, 7.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | AS7C33256NTF32A-75TQCN |
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AS7C33256NTF32A
AS7C33256NTF36A
11/8/04, v. 1.1
Alliance Semiconductor
P. 9 of 18
Timing characteristics over operating range
Snooze Mode Electrical Characteristics
Parameter
Sym
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
CENS
t
CENH
t
ADVS
t
ADVH
-75
–85
–10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
See “AC test conditions” on page 15.
Min Max Min Max Min Max
8.5
-
10
-
7.5
–
-
3.5
–
2.5
-
2.5
2.5
-
2.5
0.0
-
0
-
3.5
–
-
4.0
–
0.0
-
0
2.8
-
3.0
2.8
-
3.0
2.0
-
2.0
2.0
-
2.0
2.0
-
2.0
2.0
-
2.0
0.5
-
0.5
0.5
-
0.5
0.5
-
0.5
0.5
-
0.5
2.0
-
2.0
0.5
-
0.5
2.0
-
2.0
0.5
-
0.5
Cycle time
Clock access time
Output enable low to data valid
Clock high to output low Z
Data Output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address and Control setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
Clock enable setup to clock high
Clock enable hold from clock high
ADV setup to clock high
ADV hold from clock high
–
12
–
–
2.5
2.5
0
–
–
0
3.0
3.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
0.5
2.0
0.5
–
8.5
4.0
–
–
–
4.0
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
10
4.0
–
–
–
4.0
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2,3,4
2
2,3,4
2,3,4
2,3,4
5
5
6
6
6, 7
6, 8
6
6
6, 7
6, 8
6
6
6
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
30
Units
mA
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33256NTF32A-75TQI | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-75TQIN | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQC | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQCN | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQI | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33256NTF32A-75TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-75TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
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