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參數(shù)資料
| 型號： | AS7C33256NTF32A-75TQCN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| 中文描述： | 256K X 32 ZBT SRAM, 7.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 427K |
| 代理商： | AS7C33256NTF32A-75TQCN |
AS7C33256NTF32A
AS7C33256NTF36A
11/8/04, v. 1.1
Alliance Semiconductor
P. 6 of 18
Synchronous truth table
[5,6,7,8,9,11
]
Key
: X = Don’t Care, H = HIGH, L = LOW.
BWn = H means all byte write signals (BWa, BWb, BW
c, and
BW
d) are HIGH.
BW
n = L means one or
more byte write signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus
will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
BW
a enables WRITEs to byte “a” (DQa pins/balls);
BW
b enables WRITEs to byte “b” (DQb pins/balls);
BW
c enables WRITEs to byte “c” (DQc pins/
balls);
BW
d enables WRITEs to byte “d” (DQd pins/balls).
6 All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting
CEN
HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
CE0
H
X
X
X
L
X
L
X
L
X
L
CE1
X
X
L
X
H
X
H
X
H
X
H
CE2 ADV/LD R/W
X
L
H
L
X
L
X
H
L
L
X
H
L
L
X
H
L
L
X
H
L
L
BWn
X
X
X
X
X
X
X
X
L
L
H
OE
X
X
X
X
L
L
H
H
X
X
X
CEN
L
L
L
L
L
L
L
L
L
L
L
Address
source
NA
NA
NA
NA
External L to H
Next
External L to H NOP/DUMMY READ (Begin Burst)
Next
L to H
DUMMY READ (Continue Burst)
External L to H
WRITE CYCLE (Begin Burst)
Next
L to H
WRITE CYCLE (Continue Burst)
External L to H
NOP/WRITE ABORT (Begin Burst) High-Z
CLK
L to H
L to H
L to H
L to H
Operation
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
CONTINUE DESELECT Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
DQ
Notes
X
X
X
X
H
X
H
X
L
X
L
High-Z
High-Z
High-Z
High-Z
Q
Q
High-Z
High-Z 1,2,10
D
D
1
L to H
1,10
2
3
1,3,10
2,3
1,2,3,
10
4
X
X
X
H
X
H
X
L
Next
L to H
WRITE ABORT (Continue Burst)
High-Z
X
X
X
X
X
X
X
H
Current L to H
INHIBIT CLOCK
-
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| AS7C33256NTF32A-75TQIN | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQC | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQCN | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQI | 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33256NTF32A-75TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-75TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
| AS7C33256NTF32A-85TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD |
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