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參數(shù)資料
| 型號： | AS7C31024A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)(3.3V 128KX8 CMOS 靜態(tài)RAM（改進的引腳）) |
| 中文描述： | 3.3 128KX8 CMOS SRAM的（進化管腳）（3.3 128KX8的CMOS靜態(tài)隨機存儲器（改進的引腳）） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 113K |
| 代理商： | AS7C31024A |
AS7C1024A
AS7C31024A
2/6/01; V0.9
Alliance Semiconductor
P. 6 of 8
Data retention characteristics (over the operating range)
Parameter
Data retention waveform
AC test conditions
– Output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V
Notes
1
2
3
4
5
6
7
8
9
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except all high Z and low Z parameters, C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
This parameter is sampled and not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A, B, and C.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Symbol
Test conditions
Device
Min
Max
Unit
V
CC
for data retention
Chip deselect to data retention time
VDR
V
CC
= 2.0V
CE1
≥
V
CC
–0.2V or
CE2
≤
0.2V
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
2.0
–
V
tCDR
0
–
ns
Operation recovery time
tR
t
RC
–
–
ns
Input leakage current
| ILI |
1
μA
V
CC
CE1
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255W
C(14)
320W
D
OUT
GND
+3.3V
168W
Thevenin equivalent:
D
OUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255W
C(14)
480W
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C31024B-10JC | 3.3V 128K X 8 CMOS SRAM |
| AS7C31024B-10JCN | 8-Bit Parallel-Out Serial Shift Registers 14-TVSOP -40 to 85 |
| AS7C31024B-10STC | 8-Bit Parallel-Out Serial Shift Registers 14-TVSOP -40 to 85 |
| AS7C31024B-10STCN | 3.3V 128K X 8 CMOS SRAM |
| AS7C31024B-10TC | 8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31024A-10JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10STC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10STI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
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