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參數(shù)資料
| 型號： | AS7C31024A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)(3.3V 128KX8 CMOS 靜態(tài)RAM（改進的引腳）) |
| 中文描述： | 3.3 128KX8 CMOS SRAM的（進化管腳）（3.3 128KX8的CMOS靜態(tài)隨機存儲器（改進的引腳）） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 113K |
| 代理商： | AS7C31024A |
January 2001
Advance Information
Copyright Alliance Semiconductor. All rights reserved.
AS7C1024A
AS7C31024A
5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
2/6/01; V0.9
Alliance Semiconductor
P. 1 of 8
Features
AS7C1024A (5V version)
AS7C31024A (3.3V version)
Industrial and commercial temperatures
Organization: 131,012 words x 8 bits
High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
Low power consumption: ACTIVE
- 660 mW (AS7C1024A) / max @ 10 ns
- 324 mW (AS7C31024A) / max @ 10 ns
Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
Latest 6T 0.25u CMOS technology
2.0V data retention
Easy memory expansion with CE1, CE2, OE inputs
TTL/LVTTL-compatible, three-state I/O
32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP I
ESD protection
≥
2000 volts
Latch-up current
≥
200 mA
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
S
Input buffer
A
A
A
A
A
A
A
I/O0
I/O7
OE
CE1
CE2
WE
Column decoder
R
Control
circuit
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A
A
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A3
A2
A1
A0
I/O0
32-pin TSOP I
(8 x 20mm)
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
Selection guide
AS7C1024A-10
AS7C31024A-10
AS7C1024A-12
AS7C31024A-12
AS7C1024A-15
AS7C31024A-15
AS7C1024A-20
AS7C31024A-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
3
3
4
5
ns
Maximum
operating current
ASAS7C1024A
120
110
100
100
mA
AS7C31024A
90
80
80
80
mA
Maximum CMOS
standby current
AS7C1024A
10
10
10
15
mA
AS7C31024A
10
10
10
15
mA
相關PDF資料 |
PDF描述 |
|---|---|
| AS7C31024B-10JC | 3.3V 128K X 8 CMOS SRAM |
| AS7C31024B-10JCN | 8-Bit Parallel-Out Serial Shift Registers 14-TVSOP -40 to 85 |
| AS7C31024B-10STC | 8-Bit Parallel-Out Serial Shift Registers 14-TVSOP -40 to 85 |
| AS7C31024B-10STCN | 3.3V 128K X 8 CMOS SRAM |
| AS7C31024B-10TC | 8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31024A-10JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10STC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10STI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
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