參數(shù)資料
型號: AS7C164-15JCN
廠商: ALLIANCE MEMORY INC
元件分類: SRAM
英文描述: IC,AS7C164-15JCN,SOJ-28 ASY SRAM,15NS,8K X 8,5V
中文描述: 8K X 8 STANDARD SRAM, 15 ns, PDSO28
封裝: 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28
文件頁數(shù): 6/8頁
文件大?。?/td> 389K
代理商: AS7C164-15JCN
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1During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2
This parameter is sampled, but not 100% tested.
3
For test conditions, see AC Test Conditions, Figures A, B, and C.
4tCLZ and tCHZ are specified with CL = 5pF as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
5
This parameter is guaranteed, but not 100% tested.
6WE is High for read cycle.
7CE1 and OE are Low and CE2 is High for read cycle.
8
Address valid prior to or coincident with CE1 transition Low and CE2 transition High.
9
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to the commercial operating range only.
14 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
Parameter
Symbol
Test conditions
Min
Max
Unit
VCC for data retention
VDR
VCC = 2.0V
CE1
V
CC–0.2V or
CE2
0.2V
2.0
V
Data retention current
ICCDR
–60
A
Chip enable to data retention time
tCDR
0–
ns
Operation recovery time
tR
tRC
–ns
VCC
CE1
tR
tCDR
Data retention mode
VCC
VDR 2.0V
VIH
VDR
CS2
tR
tCDR
VIH
VDR
-Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2ns
255
C(14)
480
DRXW
GND
+5V
Figure B: 5V Output lo
DG
255
C(14)
320
DRXW
GND
+5V
Figure C: 3.3V Output load
168
Thevenin Equivalent:
DRXW
+1.728V (5V)
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