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參數(shù)資料
| 型號： | AS7C1029 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5V 256K X 4 CMOS SRAM (Center power and ground) |
| 中文描述： | 5V的256K × 4 CMOS SRAM的（中心電源和接地） |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 121K |
| 代理商： | AS7C1029 |
AS7C1029
12/5/06, v. 1.0
Alliance Memory
P. 6 of 9
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
Notes:
1
2
3
4
5
6
7
8
9
10 N/A
11
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
During V
CC
power-up, a pull-up resistor to V
CC
on
CE
is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
t
CLZ
and t
CHZ
are specified with CL = 5 pF, as in Figure B. Transition is measured
±
200 mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE
is high for read cycle.
CE
and
OE
are low for read cycle.
Address is valid prior to or coincident with
CE
transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
168
Ω
Thevenin equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
D
OUT
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
3 ns
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