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參數(shù)資料
| 型號(hào)： | AS6UA25616-100TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 100 ns, PDSO44 |
| 封裝： | 0.400 INCH, TSOP2-44 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | AS6UA25616-100TC |
2
ALLIANCE SEMICONDUCTOR
6/19/00
AS6UA25616
Functional description
The AS6UA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words x 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/70/100 ns are ideal for low-power applications. Active high and low chip enables
(CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA25616 is guaranteed not to exceed 288
W power
consumption at 3.6V and 55ns; 100
W at 2.7V and 70 ns; or 60 W at 2.3V and 100 ns. The device also returns data when V
CC is reduced
to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins
I/O0–O15 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable ( OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or wri te enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC
standard 400-mL, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care, L = Low, H = High.
Parameter
Device
Symbol
Min
Max
Unit
Voltage on VCC relative to VSS
VtIN
–0.5
VCC + 0.5
V
Voltage on any I/O pin relative to GND
VtI/O
–0.5
V
Power dissipation
PD
–1.0
W
Storage temperature (plastic)
Tstg
–65
+150
oC
Temperature with VCC applied
Tbias
–55
+125
oC
DC output current (low)
IOUT
–20
mA
CS
WE
OE
LB
UB
Supply
Current
I/O0–I/O7 I/O8–I/O15
Mode
HX
X
ISB
High Z
Standby (ISB)
LX
X
H
LH
H
X
ICC
High Z
Output disable (ICC)
LH
L
LH
ICC
DOUT
High Z
Read (ICC)
HL
High Z
DOUT
LL
DOUT
LL
X
LH
ICC
DIN
High Z
Write (ICC)
HL
High Z
DIN
LL
DIN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS6UA25616-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25616-BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25616-TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25616-TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25617 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.65V to 3.6V 256K x 16 Intelliwatt low power CMOS SRAM with two chip enables |
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