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參數(shù)資料
| 型號： | AS6UA25616-100TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 100 ns, PDSO44 |
| 封裝： | 0.400 INCH, TSOP2-44 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 206K |
| 代理商： | AS6UA25616-100TC |
Advance information
June 2000
Copyright 2000 Alliance Semiconductor. All rights reserved.
AS6UA25616
6/19/00
ALLIANCE SEMICONDUCTOR
1
1.65V to 3.6V 256K×16 Intelliwatt low-power CMOS SRAM with one chip enable
‘Features
AS6UA25616
Intelliwatt active power circuitry
Industrial and commercial temperature ranges available
Organization: 262,144 words x 16 bits
2.7V to 3.6V at 55 ns
2.3V to 2.7V at 70 ns
1.65V to 2.3V at 100 ns
Low power consumption: ACTIVE
- 54 mW at 3.6V and 55 ns
- 27 mW at 2.7V and 70 ns
- 14 mW at 2.3 V and 100 ns
Low power consumption: STANDBY
- 29 W max at 3.6V
- 11
W max at 2.7V
-9
W max at 2.3V
1.2V data retention
Equal access and cycle times
Easy memory expansion with CS, OE inputs
Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
ESD protection
≥ 2000 volts
Latch-up current
≥ 200 mA
Logic block diagram
256K × 16
Array
(4,194,304)
OE
CS
WE
Column decoder
Ro
w
D
ec
ode
r
A0
A1
A2
A3
A4
A6
A7
A8
VDD
VSS
A12
A5
A9
A1
0
A1
1
A1
4
A1
5
A1
6
A1
7
A13
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
Pin arrangement (top view)
48-CSP Ball-Grid-Array Package
123456
ALB
OE
A0
A1
A2
NC
BI/O8
UB
A3
A4
CS
I/O0
C
I/O9 I/O10
A5
A6
I/O1
I/O2
DVSS I/O11 A17
A7
I/O3
VCC
EVCC I/O12 NC
A16
I/O4
VSS
F
I/O14 I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
HNC
A8
A9
A10
A11
NC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
A0
CS
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
44-pin 400-mil TSOP II
21
22
A14
A13
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12,
shorted. The bonding of this pad to VCC or VSS configures the device. There should
only be 44+2+2 pads on the chip. Two extra VCC to separate out Array from
Peripheral and Two-Mode Pads.
Selection guide
Product
VCC Range
Speed
(ns)
Power Dissipation
Min
(V)
Typ2
(V)
Max
(V)
Operating (ICC1)Standby (ISB2)
Max (mA)
Max (
A)
AS6UA25616
2.7
3.0
3.6
55
2
20
AS6UA25616
2.3
2.5
2.7
70
1
15
AS6UA25616*
1.65
2.0
2.3
100
1
12
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS6UA25616-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25616-BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25616-TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25616-TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable |
| AS6UA25617 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.65V to 3.6V 256K x 16 Intelliwatt low power CMOS SRAM with two chip enables |
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