參數(shù)資料
型號: AS5501
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: 調(diào)制器/解調(diào)器
英文描述: ER 4C 4#8 SKT RECP BOX
中文描述: 2.4 kbps DATA, MODEM, PDSO28
封裝: SOIC-28
文件頁數(shù): 26/26頁
文件大?。?/td> 315K
代理商: AS5501
6.14 Carrier Detect - Test
VDD=5.0V, input: RXIN, output: CD
VIN_on
(CD=H, Fin=82.05kHz)
VIN_off
(CD=L, Fin=82.05kHz)
Tattack1
(CD=>H @ Vin=4.9mVrms, 82.05kHz)
Tattack2
(CD=>H @ Vin=4.9mVrms,132.45kHz)
Tattack3
(CD=>H @ Vin=4.9mVrms,132.45kHz)
Trelease1
(CD =>L @ Vin=1.5Vrms, 82.05kHz)
Trelease2
(CD=>H @ Vin=1.5Vrms, 82.05kHz)
Trelease3
(CD=>H @ Vin=1.5Vrms, 82.05kHz)
min
-
typ
-
-
max
Condition
4.9mVeff
-
9.0ms
4.5ms
2.5ms
9.0ms
5.0ms
2.5ms
M82
2.9mVeff
8.0ms
4.0ms
1.9ms
8.0ms
4.0ms
1.9ms
M82
8.33ms
4.17ms
2.08ms
-
-
-
M82, FCDON=H
M132, FCDON=L
M132, FCDON=H
M82
M82, BD1,2=H,L
M82, BD1,2=H,H
6.15 CKRX - Test
(pattern test)
The DPLL of the Rx-clock recovery circuit will be tested by a digital pattern defined during
design-phase. In Test-Mode 3 a certain DPLL-input will be supplied by the pin TST-IN. The
CLR/T has to recover a minimum of 20% jitter and a frequency tolerance of +/-1.5%.
6.16 Serial Interface - Test
(pattern test)
The serial interface will be tested by a digital pattern defined during design-phase.
min
1us
200ns
100ns
typ
-
-
-
max
-
-
-
Condition
-
-
-
Tspick
Tcssu, Tcshd
Tdsu, Tdhd
Copyright
2000, Austria Mikro Systeme International AG, SchloB Premstatten, 8141 Unterpremstatten, Austria.Tel. +43-
(0)3136-500-0, Fax +43-(0)3136-52501, E-Mail info@amsint.com
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by
any means, without the prior permission in writing by the copyright holder. To the best of its knowledge, Austria Mikro Systeme
International asserts that the information contained in this publication is accurate and correct.
AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
Rev A, May 2000
Page 25/25
相關(guān)PDF資料
PDF描述
AS5502 Multimode Powerline-Modem
AS6UA25616 2.3V to 3.6V 256K×16 Intelliwatt low-power CMOS SRAM with one chip enable(2.3V 到 3.6V 256K×16 Intelliwatt 低功耗 CMOS 靜態(tài)RAM(帶單片使能))
AS6UA25616-BC 2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable
AS6UA25616-BI 2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable
AS6UA25616-TC 2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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