參數(shù)資料
型號(hào)： AS5501
廠商： AUSTRIAMICROSYSTEMS AG
元件分類： 調(diào)制器/解調(diào)器
英文描述： ER 4C 4#8 SKT RECP BOX
中文描述： 2.4 kbps DATA, MODEM, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 10/26頁(yè)
文件大?。?/td> 315K
代理商： AS5501
There is one FREQUENCY-SYNTHESISER used to generate the
FSK-signal.
With the input signal TXD strobed with the high going edge of CKTX the control input of the
synthesiser gets modified which results in frequency shift corresponding to the data-input.
In receive-mode, the same synthesiser is used to generate the Mixer reference-clock.
The Mixer-Frequency Fmixer is set to a value to fold down the FSK-signal to one of two
possible IF-frequencies (2.7kHz / 5.4kHz).
The SCCLK-PLL is used to filter the phase jitter of the second frequency-synthesiser
generating the reference-clock for the SC-Filter. There is an external capacitor needed as
low-pass filtercomponent of the PLL-loop.
The BANDPASS Filter is used to limit the output-spectrum properly for power-line modem
applications.
The OUTPUT-STAGE is designed to be connected to an external buffer arrangement for
minimising the output-impedance and increasing the output-swing. The interface to the
external circuit is done with special I/O-pins allowed to operate with voltages up to +24V.
With two bias pins M1M and P1M the external buffer-stage gets biased (activated). When
these two pins are inactive, the buffer is in a high impedance-mode.
1.2.1 FREQ-GEN
Since the FSK-signal shall be programmable in steps of 150Hz, and the CKSYS
clock-frequency is 5.5296MHz the following structure is used for frequency generation:
The SC-CLK is defined to be 16
times the center-frequency of the
bandpass filters.
For generating the FSK or MIXER-
frequency, Fsynth gets divided by 16
for generation of proper DAC input
signals.
This means for both synthesisers the
frequency steps are 2400Hz.
To get a resolution of 2400Hz a
division by 2304 has to be done by subtraction of 2304 whenever the contents of the
SUM-REG exceeds 2303.
SUBSTR = 5529.6kHz / 2.4kHz = 2304 (=> res 2048+256)
To generate mark-frequencies in the range of 63.9 ... 140.55kHz, the adder factor Nmark has
to be:
Nmark = 16*Fmark / 2.4kHz
To cover the wanted frequency-range with a 9 bit word, a fixed number of 426 is added.
MRK-REG
Nmark = MRK-REG+426
min
0
426
max
511
937
Fout
Fmark
63.9kHz
140.55kHz
1022.4kHz
2248.8kHz
AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
Rev A, May 2000
Page 9/25
ADDER
SUM-REG
&
s
q
r
1k
2k
256
res2304
CKSYS
5.5296M
12
10
N
Fout
FSYNTH
相關(guān)PDF資料
PDF描述
AS5502 Multimode Powerline-Modem
AS6UA25616 2.3V to 3.6V 256K×16 Intelliwatt low-power CMOS SRAM with one chip enable(2.3V 到 3.6V 256K×16 Intelliwatt 低功耗 CMOS 靜態(tài)RAM（帶單片使能）)
AS6UA25616-BC 2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable
AS6UA25616-BI 2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable
AS6UA25616-TC 2.3V to 3.6V 256K】16 Intelliwatt⑩ low-power CMOS SRAM with one chip enable
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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