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| 型號： | AS4SD4M16A2-8 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 30/51頁 |
| 文件大?。?/td> | 1071K |
| 代理商： | AS4SD4M16A2-8 |
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S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
30
NOTES:
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
, V
DD
Q = +3.3V; f = 1 MHz, T
A
= 25°C; pin under test biased at 1.4V.
3. I
is dependent on output loading and cycle rates. Speci-
fied values are obtained with minimum cycle time and the out-
puts open.
4. Enables on-chip refresh and address counters.
time at which proper operation over the full temperature range
is ensured: (0°C < T
< +125°C for XT), (-40°C < T
A
< +85°C
for IT), and (-45°C < T
< +105°C for IT+).
6. An initial pause of 100μs is required after power-up, followed
by two AUTO REFRESH commands, before proper device op-
eration is ensured. (V
DD
and V
Q must be powered up simul-
taneously. V
and V
Q must be at the same potential.) The
two AUTO REFRESH command wake-ups should be repeated
any time the tREF refresh requirement is exceeded.
7. AC characteristics assume t
= 1ns.
8. In addition to meeting the transition rate specification, the
clock and CKE must transit between V
IH
and V
IL
(or between V
IL
and V
) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
10. t
defines the time at which the output achieves the open
circuit condition; it is not a reference to V
or V
. The last
valid data element will meet t
before going High-Z.
11. AC operating and I
test conditions have V
= 0V and V
IH
= 3.0V using a measurement reference level of 1.5V. If the input
transition time is longer than 1ns, then the timing is measured
from V
(MAX) and V
IH
(MIN) and no longer from the 1.5V
mid-point.
12. Other input signals are allowed to transition no more than
once every two clocks and are otherwise at valid V
IH
or V
IL
levels.
13. I
specifications are tested after the device is properly ini-
tialized.
14. Timing actually specified by t
; clock(s) specified as a
reference only at minimum cycle rate.
15. Timing actually specified by t
plus t
RP
; clock(s) specified
as a reference only at minimum cycle rate.
16. Timing actually specified by t
.
17. Required clocks are specified by JEDEC functionality and
are not dependent on any timing parameter.
18. The I
current will increase or decrease proportionally ac-
cording to the amount of frequency alteration for the test con-
dition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this
period.
21. Based on t
= 7.5ns for -75.
22. V
overshoot: V
(MAX) = V
Q = 2V for a pulse width <
3ns, and the pulse width cannot be greater than one third of the
cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width <
3ns.
23. The clock frequency must remain constant (stable clock is
defined as a signal cycling within timing constraints specified
for the clock pin) during access or precharge states (READ,
WRITE, including t
, and PRECHARGE commands). CKE
may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget
(t
) begins 7.5ns after the first clock delay, after the last WRITE
is executed. May not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clock.
27. for -75 at CL = 3 with no load is 4.6ns and is guaranteed by
design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. CL = 3 and tCK = 7.5ns.
33. CKE is HIGH during refresh command period t
(MIN) else
CKE is LOW. The I
6 limit is actually a nominal value and
does not result in a fail value.
34. 64ms refresh for IT, IT+ temperature options, 24ms refresh
for XT temperature option.
35. Self refresh mode available for IT and IT+ only.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS5010 | Voltage Reference |
| AS5010GN | Voltage Reference |
| AS5010HN | Voltage Reference |
| AS5010JT | Voltage Reference |
| AS5010KT | Voltage Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4SD4M16DG-10/IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 Meg x 16 SDRAM Synchronous DRAM Memory |
| AS4SD4M16DG-10/XT | 制造商:Micross Components 功能描述:SDRAM-SDR,64MB - Trays |
| AS4SD4M16DG-8/ET | 制造商:Micross Components 功能描述:SDRAM-SDR,64MB - Trays |
| AS4SD4M16DG-8/IT | 制造商:Micross Components 功能描述:SDRAM-SDR,64MB - Trays |
| AS4SD4M16DG-8/XT | 制造商:Micross Components 功能描述:SDRAM-SDR,64MB - Trays |
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