參數(shù)資料
型號: AS4SD4M16A2-8
英文描述: x16 SDRAM
中文描述: x16內(nèi)存
文件頁數(shù): 21/51頁
文件大小: 1071K
代理商: AS4SD4M16A2-8
S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
21
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge); A
READ to bank
m
will interrupt a WRITE on bank
n
when
registered, with the data-out appearing CAS latency later. The
PRECHARGE to bank
n
will begin after t
WR
is met, where t
WR
begins when the READ to bank
m
is registered. The last valid
WRITE to bank
n
will be data-in registered one clock prior to
the READ to bank
m
(Figure 26).
4. Interrupted by a WRITE (with or without auto precharge): A
WRITE to bank
m
will interrupt a WRITE on bank
n
when
registered. The PRECHARGE to bank
n
will begin after t
WR
is
met, where t
WR
begins when the WRITE to bank
m
is registered.
The last valid data WRITE to bank
n
will be data registered one
clock prior to the WRITE to bank
m
(Figure 26).
FIGURE 26: WRITE With Auto Precharge Interrupted by a READ
FIGURE 27: WRITE With Auto Precharge Interrupted by a WRITE
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