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S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22
TRUTH TABLE 2: CKE
1,2,3,4
CKEn-1
CKEn
CURRENT STATE
Power-Down
Self Refresh
Clock Suspend
Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
COMMANDn
X
X
X
ACTIONn
NOTES
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
COMMAND INHIBIT or NOP Exit Power-Down
COMMAND INHIBIT or NOP Exit Self Refresh
X
COMMAND INHIBIT or NOP Power-Down Entry
AUTO REFRESH
VALID
See Truth Table 3
5
6
7
Exit Clock Suspend
Self Refresh Entry
Clock Suspend Entry
H
H
L
L
H
H
L
L
NOTES:
1. CKE
n
is the logic state of CKE at clock edge
n
; CKE
n-1
was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge
n
.
3. COMMAND
n
is the command registered at clock edge
n
, and ACTION
n
is a result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge
n
will put the device in the all banks idle state in time for clock edge
n+1
(provided
that t
CKS
is met).
6. Exiting self refresh at clock edge
n
will put the device in the all banks idle state once t
XSR
is met. COMMAND INHIBIT or NOP
commands should be issued on any clock edges occurring during the t
XSR
period. A minimum of two NOP commands must be
provided during t
XSR
period.
7. After exiting clock suspend at clock edge
n
, the device will resume operation and recognize the next command at clock
edge
n+1
.