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參數(shù)資料
| 型號： | AS4LC8M8S0-8TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 566K |
| 代理商： | AS4LC8M8S0-8TC |
AS4LC8M8S0
AS4LC4M16S0
7/5/00
ALLIANCE SEMICONDUCTOR
3
Pin descriptions
Pin
Name
Description
CLK
System clock
All operations synchronized to rising edge of CLK. It also increments
the burst counters.
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. Pulling CKE
low has the following effects:
all banks idle: Precharge power down and Self refresh.
row active in any bank: Active power down.
burst/access in progress: Clock suspend.
CKE
Clock enable
When in Power down or Self refresh mode, CKE becomes
asynchronous until exiting the mode.
Enables or disables device operation by masking or enabling all inputs
except CLK, CKE, UDQM/LDQM (
×
16), DQM (
×
8).
Row and column addresses are multiplexed. Row address: A0~A11.
Column address (8M
×
8): A0~A8. Column address (4M
×
16):
A0~A7.
Memory cell array is organized in 4 banks. BA0 and BA1 select which
internal bank will be active during activate, read, write, and
precharge operations.
Enables row access and precharge operation. When
RAS
is low, row
address is latched at the rising edge of CLK.
Column address strobeEnables column access. When CAS is low, starting column address for
the burst access operation is latched at the rising edge of the CLK.
Write enable
Enables write operation and row precharge operation.
Controls I/O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
For
×
16, LDQM controls lower byte (DQ0–7) and UDQM controls
upper byte (DQ8–15). For
×
8, only one DQM controls the 8 DQs.
UDQM and LDQM are considered same state when referenced as
DQM.
Data inputs/outputs are multiplexed. Data bus for 8M
×
8 is
DQ0~DQ7 only.
Power supply/ground Power and ground for core logic and input buffers.
Data output power/
ground
CS
Chip select
A0~A11
Address
BA0, BA1
Bank select
RAS
Row address strobe
CAS
WE
×
8: DQM
×
16: UDQM/LDQM
Output disable/ write
mask
DQ0~DQ15
Data input/output
V
DD
/V
SS
V
DDQ
/V
SSQ
Power and ground for data output buffers.
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