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參數(shù)資料
| 型號： | AS4LC8M8S0-8TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 566K |
| 代理商： | AS4LC8M8S0-8TC |
AS4LC8M8S0
AS4LC4M16S0
7/5/00
ALLIANCE SEMICONDUCTOR
11
Device operation (continued)
Command
Pin Settings
Description
Burst stop
CS = WE = low; RAS =
CAS = high
Use burst stop to terminate burst operation. This command may be used
to terminate all legal burst lengths.
The Bank Precharge command precharges the bank specified by BA0 and
BA1. The precharged bank is switched from active to idle state and is
ready to be activated again. Assert the precharge command after
t
RAS
(min) of the bank activate command in the specified bank. The
precharge operation requires a time of t
RP
(min) to complete.
Bank precharge
CS = A10 = RAS = WE =
low; CAS = high; A11 =
bank select; A0~A9 =
don’t care
Precharge all
CS = RAS = WE = low;
CAS = A10 = high;
BA0~BA1 = bank select;
A0~A9 = don’t care
CS = CAS = WE (write) =
low; RAS = WE (read) =
A10 = high; BA0~BA1 =
bank select; A0~A9 =
column address; (A9 =
don’t care for 2M
×
8;
A8,A9 = don’t care for
1M
×
16)
The Precharge All command precharges all four banks simultaneously.
All four banks are switched to the idle state on precharge completion.
Auto precharge
During auto precharge, the SDRAM adjusts internal timing to satisfy
t
RAS
(min) and t
RP
for the programmed CAS latency and burst length.
Couple the auto precharge with a burst read/write operation by
asserting A10 to a high state at the same time the burst read/write
commands are issued. At auto precharge completion, the specified bank
is switched from active to idle state. Note that no new commands to the
bank can be issued until the specified bank achieves the idle state. Auto
precharge doesn’t work with full-page burst.
When CKE is low, the internal clock is frozen or suspended from the
next clock cycle and the state of the output and burst address are frozen.
If all banks are idle and CKE goes low, the SDRAM enters power down
mode at the next clock cycle. When in power down mode, no input
commands are acknowledged as long as CKE remains low. To exit power
down mode, raise CKE high before the rising edge of CLK.
Resume internal clock operation by asserting CKE high before the rising
edge of CLK. Subsequent commands can be issued one clock cycle after
the end of the Exit command.
SDRAM storage cells must be refreshed every 64ms to maintain data
integrity. Use the Auto Refresh command to refresh all rows in all banks
of the SDRAM. The row address is provided by an internal counter
which increments automatically. Auto refresh can only be asserted when
all four banks are idle and the device is not in the power down mode.
The time required to complete the auto refresh operation is t
RC
(min).
Use NOPs in the interim until the auto refresh operation is complete.
This is the most common refresh mode. It is typically performed once
every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. All
four banks will be in the idle state after this operation.
Self refresh is another mode for refreshing SDRAM cells. In this mode,
refresh address and timing are provided internally. Self refresh entry is
allowed only when all four banks are idle. The internal clock and all
input buffers with the exception of CKE are disabled in this mode. Exit
self refresh by restarting the external clock and then asserting CKE high.
NOP’s must follow for a time of t
RC
(min) for the SDRAM to reach the
idle state where normal operation is allowed. If burst auto refresh is used
in normal operation, burst 4096 auto refresh cycles immediately after
exiting self refresh.
Clock suspend/power
down mode entry
CKE = low
Clock suspend/power
down mode exit
CKE = high
Auto refresh
CS = RAS = CAS = low;
WE = CKE = high;
A0~A11 = don’t care
Self refresh
CS = RAS = CAS = CKE =
low; WE = high; A0~A11
= don’t care
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