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參數(shù)資料
| 型號(hào)： | AS4C256K16E0-30 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5V 256Kx16 CMOS DRAM (EDO) |
| 中文描述： | 5V的256Kx16的CMOS的DRAM（江戶） |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 644K |
| 代理商： | AS4C256K16E0-30 |
AS4C256K16E0
4/11/01; v.1.1
Alliance Semiconductor
7 of 24
Notes
1
2
3
I
CC1
, I
CC3
, I
CC4
, and I
CC6
depend on cycle rate.
I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
An initial pause of 200
μ
s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
AC Characteristics assume t
T
= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, V
IL
(min)
≥
GND and V
IH
(max)
≤
V
CC
.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and V
IL
.
Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by t
AA
.
Assumes three state test load (5 pF and a 380
Thevenin equivalent).
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10 t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
11 t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t
WS
≥
t
WS
(min) and t
WH
≥
t
WH
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min) and t
AWD
≥
t
AWD
(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
CAA
or t
CAC
or t
CAP
.
14 t
ASC
≥
t
CP
to achieve t
PC
(min) and t
CAP
(max) values.
15 These parameters are sampled and not 100% tested.
4
5
6
7
8
9
Key to switching waveform
Read cycle waveform
Undefined/don’t care
Falling input
Rising input
t
RAS
t
RC
t
RP
t
RSH
t
RAD
t
RCH
t
OFF
RAS
UCAS,
LCAS
Address
WE
OE
I/O
Col Address
Row Address
t
CRP
t
CSH
t
ASC
t
RCS
t
RCD
t
CAH
t
CAS
t
AR
t
RAL
t
RAH
t
AA
t
CLZ
t
RRH
Data Out
t
ASR
t
RAC
t
ROH
t
OEA
t
CAC
t
OEZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4C256K16E0-30JC | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-35 | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-35JC | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-50 | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-50JC | 5V 256Kx16 CMOS DRAM (EDO) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4C256K16E0-30JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-35 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-35JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-45JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
| AS4C256K16E0-50 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256Kx16 CMOS DRAM (EDO) |
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