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參數(shù)資料
| 型號： | AS3931 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 微波射頻器件 |
| 英文描述： | 3D Low Power Wakeup Receiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 文件頁數(shù)： | 15/30頁 |
| 文件大小： | 822K |
| 代理商： | AS3931 |
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AS3931
Datasheet - Detailed Description
8.3 Basic Operation
8.3.1 LF Transmission Protocol
8.3.1.1 Data Pattern
The AS3931 identifies a 16 half-bit binary coded data pattern, which is ASK-modulated on a LF carrier. The pattern must contain 8 LOGIC 0 half-
bits and 8 LOGIC 1 half-bits in order to be DC free. Furthermore, for a proper detector threshold adaptation it has to be ensured that there are no
long groups of LOGIC 0 and LOGIC 1 half-bits. Therefore coding of the 16 half-bit binary data to 8 Manchester bits is common. This means that
8 consecutive half-bit pairs are grouped to Manchester bits whereas a Manchester bit 1 is a HIGH to LOW transition and a Manchester bit 0 is a
LOW to HIGH transition. The AS3931 supports the Manchester bit pattern 96 [hex] which in binary code is: 10 01 01 10 01 10 10 01. MSB is
transmtted first. The Manchester bit pattern i.e. the binary DATA pattern can be changed on demand by a metal mask modification.
8.3.1.2 Double Data Pattern
To increase the immunity against parasitic wakeups, the data pattern necessary for a successful wakeup can be doubled by programmng the
AS3931: if the double data pattern is used, the pattern 96 has to be sent twice; after recognition of the first data pattern, the second data pattern
has to be sent immediately after the first one, otherwise no WAKE signal is generated. For the timng see
Wake Up Frame on page 15
. Setting
the bit M1 to 1 can programthe double data pattern feature.
8.3.1.3 Wake Up Frame
The Wake Up Frame of AS3931 consists of a preamble used for detector threshold adaptation followed by the DATA pattern once (normal or
single Wake Up) or twice (double Wake Up) to be identified. We recommend a transmssion protocol as shown on
Figure 15
and
Figure 16
. The
preamble consists of a half-bit pattern 1010... with a specified number N
PRE
of half-bits (N
PRE
must be an even number in order to get complete
1/0 pairs). N
PRE
depends on the application and has influence on the wakeup and overload sensitivity. We recommend a mnimumof N
PRE
= 8
half-bits (according to 4 manchester bits “1”).
Figure 15. Wake Up Frame of
AS3931
with Single WAKE Data Pattern
Figure 16. Wake Up Frame of
AS3931
with Double WAKE Data Pattern
Preamble
N
PRE
half
-
bits
Data 96
5.86 ms (16 half
-
bits)
WAKE
LF Carrier
Amplitude
Preamble
N
PRE
half-bits
Data 96
5.86 ms (16 halfbits)
WAKE
LF Carrier
Amplitude
Data 96
5.86 ms (16 half
-
bits)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS3932-BTST | Programmable 3D LF Receiver; Package Type: TSSOP-16; Temperature Range: -40 - +85 °C; Supply Voltage: 2,40-3,60 |
| AS3932-BQFT | Programmable 3D LF Receiver; Package Type: QFN(4x4)-16; Temperature Range: -40 - +85 °C; Supply Voltage: 2,40-3,60 |
| AS4C1M16E5 | 5V 1M×16 CMOS DRAM (EDO)(5V 1M×16 CMOS動態(tài)RAM（擴展數(shù)據(jù)總線）) |
| AS4C1M16F5 | 5V 1M×16 CMOS DRAM (Fast-page Mode)(5V 1M×16 CMOS動態(tài)RAM（快速頁面模式）) |
| AS4C256K16E0-50TC | 5V 256Kx16 CMOS DRAM (EDO) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS3931 DB | 制造商:AMS 功能描述:BOARD DEMO FOR AS3931 制造商:AMS 功能描述:Demoboard for AS3931 3D Low Power Wakeup Receiver |
| AS39310FLF | 制造商:TT Electronics / IRC 功能描述:AS39310FLF |
| AS39310HLF | 制造商:TT Electronics / IRC 功能描述:AS39310HLF |
| AS39310JLF | 制造商:TT Electronics / IRC 功能描述:AS39310JLF |
| AS39311FLF | 制造商:TT Electronics / IRC 功能描述:AS39311FLF |
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