參數(shù)資料
型號： AS1533-T
廠商： AUSTRIAMICROSYSTEMS AG
元件分類： ADC
英文描述： 12-Bit, 4-CH, ADC, 300ksps; Package Type: TSSOP-16
封裝： TSSOP-16
文件頁數(shù)： 9/28頁
文件大?。?/td> 920K
代理商： AS1533-T
www.austriamicrosystems.com
Revision 1.00
9 - 28
AS1532/AS1533
Data Sheet
- Electrical Characteristics
Timing Characteristics
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
3. Offset nulled.
4. Ground on channel; sinewave applied to all off channels.
5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
cycle.
6. The absolute voltage range for the analog inputs (CH0:CH3, and COM) is from GND to V
DD1
.
7. External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA
is a result of production test limitations.
8. AS1532/AS1533 performance is limited by the device noise floor, typically 300μVp-p.
9. Electrical characteristics are guaranteed from V
DD1(MIN)
= V
DD2(MIN)
= V
DD3(MIN)
to V
DD1(MAX)
= V
DD2(MAX)
=
V
DD3(MAX)
. For operations beyond this range, see
Typical Operating Characteristics on page 11
. For guaranteed
specifications beyond the limits, contact austriamicrosystems, AG.
10. AIN = mid-scale; bit
RANGE (page 15)
= 1; tested with 20pF on DOUT, 20pF on SSTRB, and f
SCLK
= 4.8MHz
@ GND to V
DD2
.
11. SCLK = DIN = GND, CSN = V
DD2
.
Table 5. AS1532 Timing Characteristics – (Figures
3
,
4
,
21
,
23
; V
DD1
= V
DD2
= V
DD3
= +4.5 to +5.5V; T
AMB
= T
MIN
to
T
MAX
(unless otherwise specified).
Symbol
Parameter
t
CP
SCLK Period
t
CH
SCLK Pulse Width High
t
CL
SCLK Pulse Width Low
t
DS
DIN to SCLK Setup
t
DH
DIN to SCLK Hold
t
CSS
CSN Fall to SCLK Rise Setup
t
CS0
SCLK Rise to CSN Fall Ignore
t
DOH
SCLK Rise to DOUT Hold
t
STH
SCLK Rise to SSTRB Hold
t
STV
SCLK Rise to DOUT Valid
t
DOV
SCLK Rise to SSTRB Valid
t
DOD
CSN Rise to DOUT Disable
t
STD
CSN Rise to SSTRB Disable
t
DOE
CSN Fall to DOUT Enable
t
STE
CSN Fall to SSTRB Enable
t
CSW
CSN Pulse Width High
Conditions
Min
156
62
62
35
0
35
35
10
10
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
20
20
80
80
65
65
65
65
10
10
100
Table 6. AS1533 Timing Characteristics – (Figures
3
,
4
,
21
,
23
; V
DD1
= V
DD2
= V
DD3
= +2.7 to +3.6V; T
AMB
= T
MIN
to
T
MAX
(unless otherwise specified).
Symbol
Parameter
t
CP
SCLK Period
t
CH
SCLK Pulse Width High
t
CL
SCLK Pulse Width Low
t
DS
DIN to SCLK Setup
t
DH
DIN to SCLK Hold
t
CSS
CSN Fall to SCLK Rise Setup
t
CS0
SCLK Rise to CSN Fall ignore
t
DOH
SCLK Rise to DOUT Hold
t
STH
SCLK Rise to SSTRB Hold
Conditions
Min
208
83
83
45
0
45
45
13
13
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
LOAD
= 20pF
C
LOAD
= 20pF
20
20
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