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參數(shù)資料
| 型號： | AOD606L |
| 廠商： | ALPHA |
| 英文描述： | Complementary Enhancement Mode Field Effect Transistor |
| 中文描述： | 增強模式互補場效應(yīng)晶體管 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 215K |
| 代理商： | AOD606L |
AOD606
Symbol
STATIC PARAMETERS
Min
Typ
Max
Units
BV
DSS
40
V
1
5
T
J
=55°C
I
GSS
V
GS(th)
I
D(ON)
100
3
nA
V
A
1
30
2.3
27
39
37
25
0.76
33
52
47
T
J
=125°C
m
g
FS
V
SD
I
S
DYNAMIC PARAMETERS
S
V
A
1
8
C
iss
C
oss
C
rss
R
g
SWITCHING PARAMETERS
Total Gate Charge
Total Gate Charge
404
95
37
2.7
pF
pF
pF
Q
g
(10V)
Q
g
(4.5V)
Q
gs
Q
gd
t
D(on)
t
r
t
D(off)
t
f
t
rr
Q
rr
9.2
4.5
1.6
2.6
3.5
6
13.2
3.5
22.9
18.3
nC
nC
nC
nC
ns
ns
ns
ns
ns
nC
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge I
F
=8A, dI/dt=100A/
μ
s
Drain-Source Breakdown Voltage
On state drain current
I
D
=10mA, V
GS
=0V
V
DS
=32V, V
GS
=0V
V
GS
=10V, V
DS
=5V
V
GS
=10V, I
D
=8A
Reverse Transfer Capacitance
Gate resistance
I
F
=8A, dI/dt=100A/
μ
s
V
GS
=0V, V
DS
=20V, f=1MHz
N-Channel MOSFET Electrical Characteristics (T
J
=25°C unless otherwise noted)
Parameter
Conditions
I
DSS
μ
A
Gate Threshold Voltage
V
DS
=V
GS
,
I
D
=250
μ
A
V
DS
=0V, V
GS
=±20V
Zero Gate Voltage Drain Current
Gate-Body leakage current
R
DS(ON)
Static Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Maximum Body-Diode Continuous Current
m
V
GS
=4.5V, I
D
=6A
V
DS
=5V, I
D
=8A
I
S
=1A, V
GS
=0V
V
GS
=0V, V
DS
=0V, f=1MHz
Turn-Off Fall Time
V
GS
=10V, V
DS
=20V, I
D
=8A
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Input Capacitance
Output Capacitance
V
GS
=10V, V
DS
=20V, R
L
=2.5
,
R
GEN
=3
A: The value of R
θ
JA
is measured with the device mounted on 1in
2
FR-4 board with 2oz. Copper, in a still air environment with T
A
=25°C. The
Power dissipation P
DSM
is based on R
θ
JA
and the maximum allowed junction temperature of 150°C. The value in any given application depends on
the user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
B. The power dissipation P
D
is based on T
J(MAX)
=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C: Repetitive rating, pulse width limited by junction temperature T
J(MAX)
=175°C.
D. The R
θ
JA
is the sum of the thermal impedence from junction to case R
θ
JC
and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300
μ
s pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a
maximum junction temperature of T
J(MAX)
=175°C.
G. The maximum current rating is limited by bond-wires.
H. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T
A
=25°C. The SOA
curve provides a single pulse rating.
Rev 0: January 2006
Alpha & Omega Semiconductor, Ltd.
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