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參數(shù)資料
| 型號： | AND8112 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | A Quasi-Resonant SPICE Model Eases Feedback Loop Designs |
| 中文描述： | 阿準(zhǔn)諧振SPICE模型反饋環(huán)的設(shè)計(jì)更易 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 205K |
| 代理商： | AND8112 |
AND8112/D
http://onsemi.com
9
Putting the Model to Work
Different ways exist to test the validity of a model. The
first one is by using SPICE only, where one can compare the
transient response of the averaged model versus that of the
equivalent cyclebycycle. The other one implies the
comparison of the averaged model results versus a real board
measurement. In this paper, we will depict both approaches,
using our simplified cyclebycycle transient model.
The averaged template is depicted by Figure 11 where
Figure 10 sources have been pushed into a single graphic
symbol. The symbol must be fed by Lp, Efficiency, R
sense
,
transformer turn ratio and the primary inductance ohmic
loss. The FB pin goes to a component arrangement particular
to the NCP1207 series from ON Semiconductor where the
optocoupler collector is internally pulledup to a reference
voltage.
9
17
3
R8
60 m
1
R1
1 k
2
D4
BV = 15.6
Fb
C5
1 n
24
L3
2.2
R6
10 m
25
R7
150 m
6
R10
20 k
V9
4.8
FB
FB
Flyback FreeRunning
Averaged model
IN
FB
GND
OUT
X1
SFH615AGR
120
16.8
16.8
16.8
16.7
15.8
1.30
16.8
16.8
4.80
Figure 11. Averaged Model Template
V
in
V
out
V
out
V
out
R
load
8.5
C4
220
I
C
=
C3
1 mF
I
C
= 16
X2
QuasiFly
L
P
= 1.2 m
R
S
= 0.5
N = 0.06
eff = 0.91
Rlf = 0.5
V
g
120
AC =
0.868
i
P
8.68
t
on
80.7
f
SW
t
on
f
SW
(kHz)
I
P
The averaged model template featuring DC bias points which confirms the correct bias point calculation
In Figure 11, once the simulation has been done, DC
points are reflected to the schematic and confirm the validity
of the original calculation. The feedback loop is made of a
simple Zener diode to avoid any long feedback time
constants as with a standard TL431. The cyclebycycle
circuitry uses our simplified QR transient model which
emulates
a
freerunning
ON Semiconductor NCP1207 or NCP1205 [3] (Figure 12).
The output stage and feedback configuration conforms to
Figure 11 in order to compare similar topologies. The first
test consists in testing the input audio susceptibility by
stepping the input voltage from 200 V to 350 VDC.
controller
such
as
Figure 13 reveals the good agreement between the averaged
response and the cyclebycycle one. The next experience
will step load the converter output from light to heavy load
in a few s. Figure 14 testifies for the right behavior on both
configuration, average or cyclebycycle.
On the static point of view, the following data compare
numbers given by the averaged model and the
cyclebycycle one:
I
P
AVG = 868 mA / I
P
TRAN = 858 mA
T
on
AVG = 8.68 s / T
on
TRAN = 8.78 s
F
SW
AVG = 80.7 kHz / F
SW
AVG = 77.8 kHz
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