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參數(shù)資料
| 型號(hào)： | AND8112 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | A Quasi-Resonant SPICE Model Eases Feedback Loop Designs |
| 中文描述： | 阿準(zhǔn)諧振SPICE模型反饋環(huán)的設(shè)計(jì)更易 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 205K |
| 代理商： | AND8112 |
AND8112/D
http://onsemi.com
11
The bandwidth measurement has been carried on a board further to a 15 mn warmup. This board does not use any clamping
network but a 800 V MOSFET instead and a large capacitor connected between drain and ground Figure 16 and 17 compare
the obtained results with the averaged model including valley and turnoff delays:
1
10
100
1 k
10 k
100 k
180
90.0
0
90.0
180
60.0
40.0
20.0
0
20.0
Figure 16. Bode Plot Captured with a Network Analyzer
Figure 17. Bode Plot Obtained with the Averaged Model
Openloop Phase:
High Line
Low Line
Openloop Gain:
High Line
Low Line
F0 dB = 46 Hz
10 k
1 k
100
10
1
20
10
0
10
20
30
40
50
60
Mag (dB)
180
Phase (
°
)
135
90
45
0
45
90
135
180
F0 dB = 49 Hz
High Line
Low Line
High Line
Low Line
One can detect a slight gain difference (around 3.5 dB) in
DC but the overall simulated shape stays in good agreement
with the real measurement. The phase dips are imputed to
the presence of the LC network whose cutoff frequency
obviously affects the results. The smallsignal analysis
details are available in [5].
Finally, a stepload response was performed on a real
board fed back by a TL431 network and compared to our
SPICE model, also implementing the same control loop
structure. Results prove that the proposed model accuracy is
acceptable to predict board stability and final transient
response:
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