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參數(shù)資料
| 型號： | AND8020D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結構 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 168K |
| 代理商： | AND8020D |
AND8020/D
http://onsemi.com
5
TERMINATION OF ECL LOGIC DEVICES
SECTION 2. PARALLEL TERMINATION EXTERNAL AND INTERNAL
R
t
R
t
External
Internal
Near (Standard Pair)
Far (Standard Pair)
Near (Standard Pair)
Far (Standard Pair)
V
EE
R
t
V
TT
Vt
R
t
R
t
R
t
R
t
Vt1
Vt2
R
t
R
t
R
t
R
t
Vt1
Vt2
V
EE
V
to
(Open)
V
EE
(Shorted)
V
TT
V
TT
R
E
R
E
R
E
R
E
R
E
R
E
Parallel termination advantages:
Method of choice for best circuit performance
Particularly excellent for driving distributed loads
Undistorted waveform along the full length of the line
Decreased power consumption.
Far DC Current Return V
TT
A parallel terminated line is one in which the receiving end
is signal terminated internally or externally (usually to a
voltage V
TT
) through a resistor (R
t
) with a value equal to the
line characteristic impedance (Figure 4). This line also carries
the biasing current for the drivers output far from the driver.
Output current and power dissipation is decreased due to use
of a V
TT
termination supply. The V
TT
supply must sustain the
emitter follower output transistor in its active operating region
under all operating conditions. A minimum continuous current
occurs for the most negative V
OL
, therefore the V
TT
supply
must remain more negative than the worst case V
OLmin
and
always sink current.
Standard V
TT
is 2.0 V below V
CC
supply. A parallel
resistor, R
t
, matching the controlled impedance transmission
line, Z
0
, connects the signal to the V
TT
supply. The Parallel
Termination to V
TT
is shown in Figure 4. The termination
resistors may be internal or external and either ganged into a
Combo pin or offered as Singulated pins. Some devices may
have each internal resistors independently pinned out,
allowing further termination versatility.
Figure 4. Parallel Termination to V
TT
Differential and SingleEnded with Combo or Singulated Vt Pins (Far Return)
V
TT
R
t
= Z
0
V
TT
=
V
CC
2.0 V
TLine Z
0
V
TT
(*or twisted pair)
Driver
Receiver
*TLine Z
0
*TLine Z
0
V
TT
R
R
(*or twisted pair)
Driver
Receiver
*TLine Z
0
*TLine Z
0
Vt
Driver
Receiver
External (Far, Diff.)
Internal Termination Combo Pin (Far, Diff.)
V
TT
R
R
(*or twisted pair)
Driver
Receiver
*TLine Z
0
*TLine Z
0
Vt1
Vt2
Internal Termination Singulated Pins (Far, Diff.)
R
t
R
t
R
t
External (Far, S.E.)
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