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參數(shù)資料
| 型號(hào)： | AND8020D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結(jié)構(gòu) |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020D |
Semiconductor Components Industries, LLC, 2004
July, 2004 Rev. 5
1
Publication Order Number:
AND8020/D
AND8020/D
Termination of ECL
Logic Devices with
EF (Emitter Follower)
OUTPUT Structure
Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering
CONTENTS OF APPLICATION NOTE
Introduction DC Termination Analysis
Vt
R
t
R
t
R
t
R
t
R
t
R
t
Vt1
Vt2
External
Internal
Near (Standard Pair)
Far (Standard Pair)
Far (Standard Pair)
V
EE
R
t
R
t
R
t
R
t
R
t
Vt1
Vt2
V
EE
V
(Open)
V
EE
(Shorted)
V
TT
Near (Standard Pair)
V
TT
V
TT
R
E
V
EE
Section 2. Parallel Termination External and Internal
Section 1. Unterminated Lines
R
R
R
R
Section 3. Thevenin Equivalent/Parallel Termination
R
R
Section 4. Series (Back) Termination
V
BB
V
BB
Driver
Receiver
*All Media
*
*
D1
D2
D1
D2
Section 5. Diode Termination
R
R
R
R
R
V
CC
V
BB
Section 6. Capacitive Coupling
R
E
R
E
R
E
R
E
R
E
R
E
R
E
R
E
APPLICATION NOTE
http://onsemi.com
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